soc/intel/baytrail: Use sb/intel/common/spi.c

This common implementation is compatible.

Change-Id: I2023bb7522ec40f1d9911cb5c57d7d66e4cefa6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/baytrail/Makefile.inc

@@ -12,12 +12,10 @@ subdirs-y += ../../../cpu/intel/common
 romstage-y += iosf.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
-romstage-y += spi.c
 romstage-y += tsc_freq.c
 
 postcar-y += iosf.c
 postcar-y += memmap.c
-postcar-y += spi.c
 postcar-y += tsc_freq.c
 
 ramstage-y += acpi.c
@@ -43,7 +41,6 @@ ramstage-y += scc.c
 ramstage-y += sd.c
 ramstage-y += smm.c
 ramstage-y += southcluster.c
-ramstage-y += spi.c
 ramstage-y += tsc_freq.c
 ramstage-y += xhci.c
 ramstage-$(CONFIG_ELOG) += elog.c
@@ -52,7 +49,6 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
 smm-y += iosf.c
 smm-y += pmutil.c
 smm-y += smihandler.c
-smm-y += spi.c
 smm-y += tsc_freq.c
 
 # Remove as ramstage gets fleshed out