soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -428,13 +428,11 @@ static void pch_cg_init(struct device *dev)
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static void pch_set_acpi_mode(void)
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{
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#if CONFIG(HAVE_SMI_HANDLER)
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if (!acpi_is_wakeup_s3()) {
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if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
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printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
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outb(APM_CNT_ACPI_DISABLE, APM_CNT);
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printk(BIOS_DEBUG, "done.\n");
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}
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#endif /* CONFIG_HAVE_SMI_HANDLER */
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}
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static void lpc_init(struct device *dev)
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@@ -141,12 +141,9 @@ asmlinkage void car_stage_entry(void)
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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#if CONFIG(HAVE_SMI_HANDLER)
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void *smm_base;
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size_t smm_size;
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uintptr_t tseg_base;
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#endif
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console_init();
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@@ -177,7 +174,6 @@ asmlinkage void car_stage_entry(void)
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/* Cache the memory-mapped boot media. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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#if CONFIG(HAVE_SMI_HANDLER)
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/*
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* Cache the TSEG region at the top of ram. This region is
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* not restricted to SMM mode until SMM has been relocated.
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@@ -185,10 +181,11 @@ asmlinkage void car_stage_entry(void)
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* when relocating the SMM handler as well as using the TSEG
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* region for other purposes.
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*/
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smm_region(&smm_base, &smm_size);
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tseg_base = (uintptr_t)smm_base;
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postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
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#endif
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if (CONFIG(HAVE_SMI_HANDLER)) {
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smm_region(&smm_base, &smm_size);
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tseg_base = (uintptr_t)smm_base;
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postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
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}
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run_postcar_phase(&pcf);
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}
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@@ -487,9 +487,8 @@ static void post_mp_init(void)
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smm_southbridge_enable(GBL_EN);
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/* Lock down the SMRAM space. */
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#if CONFIG(HAVE_SMI_HANDLER)
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smm_lock();
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#endif
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if (CONFIG(HAVE_SMI_HANDLER))
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smm_lock();
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mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC);
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