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Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"

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Don't need this additional 2ms delay as PCR read after sideband write
help to fix original hard hang issue.

This reverts commit d4b6ac19b0.

Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
2017-07-04 16:03:24 +05:30
committed by Duncan Laurie
parent 1914337936
commit b5c5b9dc7c
1 changed files with 0 additions and 2 deletions
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2
src/soc/intel/skylake/acpi/scs.asl
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@@ -86,7 +86,6 @@ Device (EMMC)
/* Set bits 31, 6, 2, 0 */ /* Set bits 31, 6, 2, 0 */
^^PCRO (PID_SCS, 0x600, 0x80000045) ^^PCRO (PID_SCS, 0x600, 0x80000045)
Sleep (2)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)
@@ -140,7 +139,6 @@ Device (SDXC)
/* Set bits 8, 7, 2, 0 */ /* Set bits 8, 7, 2, 0 */
^^PCRO (PID_SCS, 0x600, 0x00000185) ^^PCRO (PID_SCS, 0x600, 0x00000185)
Sleep (2)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)