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amd/stoneyridge: Enable SMM in TSEG

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Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.

SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size.  Add relocation attributes to be set by each
core a relocation handler.

Modify the definition of smi_southbridge_handler() to match TSEG
prototype.

BUG=b:62103112

Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marshall Dawson
2017-09-13 17:47:31 -06:00
committed by Aaron Durbin
parent f7bcc180eb
commit b617211910
6 changed files with 146 additions and 4 deletions
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8
src/soc/amd/stoneyridge/northbridge.c
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@@ -415,6 +415,8 @@ void domain_set_resources(device_t dev)
u32 hole;
int idx;
struct bus *link;
void *tseg_base;
size_t tseg_size;
pci_tolm = 0xffffffffUL;
for (link = dev->link_list ; link ; link = link->next)
@@ -505,6 +507,12 @@ void domain_set_resources(device_t dev)
*/
mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);
reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
/* Reserve TSEG */
smm_region_info(&tseg_base, &tseg_size);
idx += 0x10;
reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB,
tseg_size/KiB);
}
/*********************************************************************