diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 007fa9669e..457383d734 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -13,9 +13,11 @@
 #include <option.h>
 #include <intelblocks/irq.h>
 #include <intelblocks/lpss.h>
+#include <intelblocks/mp_init.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
+#include <intelblocks/systemagent.h>
 #include <intelblocks/tcss.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
@@ -917,6 +919,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
  * Phase   |  FSP return point                                |  Purpose
  * ------- + ------------------------------------------------ + -------------------------------
  *   1     |  After TCSS initialization completed             |  for TCSS specific init
+ *   2     |  Before BIOS Reset CPL is set by FSP-S           |  for CPU specific init
  */
 void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
 {
@@ -931,6 +934,14 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
 			tcss_configure(config->typec_aux_bias_pads);
 		}
 		break;
+	case 2:
+		/* CPU specific initialization here */
+		printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
+			__FILE__, __func__);
+		before_post_cpus_init();
+		/* Enable BIOS Reset CPL */
+		enable_bios_reset_cpl();
+		break;
 	default:
 		break;
 	}