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indent files to reduce the noise in further diffs.

Browse Source 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2004-04-24 23:25:56 +00:00
parent 234454d900
commit b6ce3ec68c
4 changed files with 192 additions and 146 deletions
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18
src/mainboard/amd/solo/auto.c
View File

@ -43,13 +43,15 @@ static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
/* Set the memreset low */ /* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */ /* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
} (0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
else { } else {
/* Ensure the CPU has controll of the memory lines */ /* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} }
} }
@ -58,12 +60,14 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
udelay(800); udelay(800);
/* Set memreset_high */ /* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90); udelay(90);
} }
} }
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) static unsigned int generate_row(uint8_t node, uint8_t row,
uint8_t maxnodes)
{ {
/* since the AMD Solo is a UP only machine, we can /* since the AMD Solo is a UP only machine, we can
* always return the default row entry value * always return the default row entry value

4
src/mainboard/amd/solo/mainboard.c
View File

@ -11,8 +11,7 @@
#include "chip.h" #include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] = unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
{
0, 0,
}; };
@ -39,4 +38,3 @@ struct chip_control mainboard_amd_solo_control = {
.enumerate = enumerate, .enumerate = enumerate,
.name = "AMD Solo7 mainboard ", .name = "AMD Solo7 mainboard ",
}; };

148
src/mainboard/amd/solo/mptable.c
View File

@ -42,14 +42,18 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* 8111 */ /* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x04, 0)); dev = dev_find_slot(1, PCI_DEVFN(0x04, 0));
if (dev) { if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8111_1 =
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa =
pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
printk_debug(" mptable: 8111 PCI bus %d\n", bus_8111_1); printk_debug(" mptable: 8111 PCI bus %d\n",
printk_debug(" mptable: 8111 ISA bus %d\n", bus_isa); bus_8111_1);
} printk_debug(" mptable: 8111 ISA bus %d\n",
else { bus_isa);
printk_debug("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n"); } else {
printk_debug
("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
bus_8111_1 = 3; bus_8111_1 = 3;
bus_isa = 4; bus_isa = 4;
@ -57,11 +61,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* 8151-1 */ /* 8151-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01, 0)); dev = dev_find_slot(1, PCI_DEVFN(0x01, 0));
if (dev) { if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8151_1 =
printk_debug(" mptable: 8151 PCI bus %d\n", bus_8151_1); pci_read_config8(dev, PCI_SECONDARY_BUS);
} printk_debug(" mptable: 8151 PCI bus %d\n",
else { bus_8151_1);
printk_debug("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n"); } else {
printk_debug
("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
bus_8151_1 = 2; bus_8151_1 = 2;
} }
@ -78,110 +84,148 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000); smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
/* ISA backward compatibility interrupts */ /* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, 0x02, 0x00); bus_isa, 0x00, 0x02, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x01, 0x02, 0x01); bus_isa, 0x01, 0x02, 0x01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, 0x02, 0x02); bus_isa, 0x00, 0x02, 0x02);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x03, 0x02, 0x03); bus_isa, 0x03, 0x02, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x04, 0x02, 0x04); bus_isa, 0x04, 0x02, 0x04);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x05, 0x02, 0x05); bus_isa, 0x05, 0x02, 0x05);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x06, 0x02, 0x06); bus_isa, 0x06, 0x02, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x07, 0x02, 0x07); bus_isa, 0x07, 0x02, 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x08, 0x02, 0x08); bus_isa, 0x08, 0x02, 0x08);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x09, 0x02, 0x09); bus_isa, 0x09, 0x02, 0x09);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0a, 0x02, 0x0a); bus_isa, 0x0a, 0x02, 0x0a);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0b, 0x02, 0x0b); bus_isa, 0x0b, 0x02, 0x0b);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0c, 0x02, 0x0c); bus_isa, 0x0c, 0x02, 0x0c);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0d, 0x02, 0x0d); bus_isa, 0x0d, 0x02, 0x0d);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0e, 0x02, 0x0e); bus_isa, 0x0e, 0x02, 0x0e);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0f, 0x02, 0x0f); bus_isa, 0x0f, 0x02, 0x0f);
/* Standard local interrupt assignments */ /* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x00); bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x01); bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* AGP Slot */ /* AGP Slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8151_1, (0 << 2) | 0, 0x02, 0x10); bus_8151_1, (0 << 2) | 0, 0x02, 0x10);
/* PCI Slot 1 */ /* PCI Slot 1 */
#warning "FIXME get the irqs right, it's just hacked to work for now" #warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 0, 0x02, 0x10); bus_8111_1, (4 << 2) | 0, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 1, 0x02, 0x11); bus_8111_1, (4 << 2) | 1, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 2, 0x02, 0x12); bus_8111_1, (4 << 2) | 2, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 3, 0x02, 0x13); bus_8111_1, (4 << 2) | 3, 0x02, 0x13);
/* PCI Slot 2 */ /* PCI Slot 2 */
#warning "FIXME get the irqs right, it's just hacked to work for now" #warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 0, 0x02, 0x11); bus_8111_1, (5 << 2) | 0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 1, 0x02, 0x12); bus_8111_1, (5 << 2) | 1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 2, 0x02, 0x13); bus_8111_1, (5 << 2) | 2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 3, 0x02, 0x10); bus_8111_1, (5 << 2) | 3, 0x02, 0x10);
/* PCI Slot 3 */ /* PCI Slot 3 */
#warning "FIXME get the irqs right, it's just hacked to work for now" #warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 0, 0x02, 0x12); bus_8111_1, (6 << 2) | 0, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 1, 0x02, 0x13); bus_8111_1, (6 << 2) | 1, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 2, 0x02, 0x10); bus_8111_1, (6 << 2) | 2, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 3, 0x02, 0x11); bus_8111_1, (6 << 2) | 3, 0x02, 0x11);
/* PCI Slot 4 */ /* PCI Slot 4 */
#warning "FIXME get the irqs right, it's just hacked to work for now" #warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 0, 0x02, 0x13); bus_8111_1, (7 << 2) | 0, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 1, 0x02, 0x10); bus_8111_1, (7 << 2) | 1, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 2, 0x02, 0x11); bus_8111_1, (7 << 2) | 2, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 3, 0x02, 0x12); bus_8111_1, (7 << 2) | 3, 0x02, 0x12);
/* Local devices */ /* Local devices */
/* USB */ /* USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_8111_1, (0 << 2) | 3, 0x02, 0x13); bus_8111_1, (0 << 2) | 3, 0x02, 0x13);
/* Sound */ /* Sound */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
1, (5 << 2) | 1, 0x02, 0x11); 1, (5 << 2) | 1, 0x02, 0x11);
/* There is no extension information... */ /* There is no extension information... */
/* Compute the checksums */ /* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n", printk_debug("Wrote the mp table end at: %p - %p\n",
@ -189,10 +233,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc); return smp_next_mpe_entry(mc);
} }
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map) unsigned long write_smp_table(unsigned long addr,
unsigned long *processor_map)
{ {
void *v; void *v;
v = smp_write_floating_table(addr); v = smp_write_floating_table(addr);
return (unsigned long) smp_write_config_table(v, processor_map); return (unsigned long) smp_write_config_table(v, processor_map);
} }