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indent files to reduce the noise in further diffs.

Browse Source 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2004-04-24 23:25:56 +00:00
parent 234454d900
commit b6ce3ec68c
4 changed files with 192 additions and 146 deletions
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24
src/mainboard/amd/solo/auto.c
View File

@ -43,13 +43,15 @@ static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
else {
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -58,12 +60,14 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
static unsigned int generate_row(uint8_t node, uint8_t row,
uint8_t maxnodes)
{
/* since the AMD Solo is a UP only machine, we can
* always return the default row entry value
@ -94,8 +98,8 @@ static void main(void)
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|1, 0, 0 },
.channel1 = { 0, 0, 0, 0 },
.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1, 0, 0},
.channel1 = {0, 0, 0, 0},
}
};
int needs_reset;
@ -127,7 +131,7 @@ static void main(void)
dump_spd_registers(&cpu[0]);
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();

20
src/mainboard/amd/solo/irq_tables.c
View File

@ -20,7 +20,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
32 + 16 * IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
* devices on the bus */
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
@ -28,7 +28,7 @@ const struct irq_routing_table intel_irq_routing_table = {
IRQ_ROUTER_VENDOR, /* Vendor */
IRQ_ROUTER_DEVICE, /* Device */
0x00, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , mod 256 checksum must give
* zero, will be corrected later
*/
@ -37,18 +37,18 @@ const struct irq_routing_table intel_irq_routing_table = {
/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
/* PCI SLOT 1-4 */
IRQ_SLOT (1, 3,4,0, 1,2,3,4 ),
IRQ_SLOT (2, 3,5,0, 2,3,4,1 ),
IRQ_SLOT (3, 3,6,0, 3,4,1,2 ),
IRQ_SLOT (4, 3,7,0, 4,1,2,3 ),
IRQ_SLOT(1, 3, 4, 0, 1, 2, 3, 4),
IRQ_SLOT(2, 3, 5, 0, 2, 3, 4, 1),
IRQ_SLOT(3, 3, 6, 0, 3, 4, 1, 2),
IRQ_SLOT(4, 3, 7, 0, 4, 1, 2, 3),
/* Builtin Devices */
IRQ_SLOT (0, 3,0,0, 4,4,4,4 ), /* USB */
IRQ_SLOT (0, 1,5,1, 1,2,3,4 ), /* IDE */
IRQ_SLOT (0, 1,2,0, 1,2,3,4 ), /* AGP Bridge */
IRQ_SLOT(0, 3, 0, 0, 4, 4, 4, 4), /* USB */
IRQ_SLOT(0, 1, 5, 1, 1, 2, 3, 4), /* IDE */
IRQ_SLOT(0, 1, 2, 0, 1, 2, 3, 4), /* AGP Bridge */
/* Let Linux know about bus 1 */
IRQ_SLOT (0, 1,5,0, 0,0,0,0 ),
IRQ_SLOT(0, 1, 5, 0, 0, 0, 0, 0),
}
};

6
src/mainboard/amd/solo/mainboard.c
View File

@ -11,8 +11,7 @@
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{
unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
0,
};
@ -31,7 +30,7 @@ static void enumerate(struct chip *chip)
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
for (child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
@ -39,4 +38,3 @@ struct chip_control mainboard_amd_solo_control = {
.enumerate = enumerate,
.name = "AMD Solo7 mainboard ",
};

198
src/mainboard/amd/solo/mptable.c
View File

@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v, unsigned long * processor_map)
void *smp_write_config_table(void *v, unsigned long *processor_map)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
@ -15,7 +15,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
unsigned char bus_8151_1;
unsigned char bus_8111_1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mc = (void *) (((char *) v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
@ -40,35 +40,41 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
printk_info("creating mp table...\n");
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x04,0));
dev = dev_find_slot(1, PCI_DEVFN(0x04, 0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_8111_1 =
pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa =
pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
printk_debug(" mptable: 8111 PCI bus %d\n", bus_8111_1);
printk_debug(" mptable: 8111 ISA bus %d\n", bus_isa);
}
else {
printk_debug("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
printk_debug(" mptable: 8111 PCI bus %d\n",
bus_8111_1);
printk_debug(" mptable: 8111 ISA bus %d\n",
bus_isa);
} else {
printk_debug
("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
bus_8111_1 = 3;
bus_isa = 4;
}
/* 8151-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
dev = dev_find_slot(1, PCI_DEVFN(0x01, 0));
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
printk_debug(" mptable: 8151 PCI bus %d\n", bus_8151_1);
}
else {
printk_debug("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
bus_8151_1 =
pci_read_config8(dev, PCI_SECONDARY_BUS);
printk_debug(" mptable: 8151 PCI bus %d\n",
bus_8151_1);
} else {
printk_debug
("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
bus_8151_1 = 2;
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
for (bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
@ -78,110 +84,148 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
/* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, 0x02, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x01, 0x02, 0x01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, 0x02, 0x02);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x03, 0x02, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x04, 0x02, 0x04);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x05, 0x02, 0x05);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x06, 0x02, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x07, 0x02, 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x08, 0x02, 0x08);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x09, 0x02, 0x09);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0a, 0x02, 0x0a);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0b, 0x02, 0x0b);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0c, 0x02, 0x0c);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0d, 0x02, 0x0d);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0e, 0x02, 0x0e);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x0f, 0x02, 0x0f);
/* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* AGP Slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8151_1, (0<<2)|0, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8151_1, (0 << 2) | 0, 0x02, 0x10);
/* PCI Slot 1 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|0, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|1, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|2, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|3, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 0, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 1, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 2, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4 << 2) | 3, 0x02, 0x13);
/* PCI Slot 2 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|3, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5 << 2) | 3, 0x02, 0x10);
/* PCI Slot 3 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|0, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|1, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|2, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|3, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 0, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 1, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 2, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6 << 2) | 3, 0x02, 0x11);
/* PCI Slot 4 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|0, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|1, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|2, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|3, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 0, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 1, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 2, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7 << 2) | 3, 0x02, 0x12);
/* Local devices */
/* USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_8111_1, (0<<2)|3, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_8111_1, (0 << 2) | 3, 0x02, 0x13);
/* Sound */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
1, (5<<2)|1, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
1, (5 << 2) | 1, 0x02, 0x11);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
@ -189,10 +233,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
unsigned long write_smp_table(unsigned long addr,
unsigned long *processor_map)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v, processor_map);
return (unsigned long) smp_write_config_table(v, processor_map);
}