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Add support for storing POST codes in CMOS

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This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.

The active bank is switched early in the bootblock.

Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD

Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie
2012-09-09 19:09:56 -07:00
committed by Stefan Reinauer
parent 31409617a4
commit b6e97b19ae
5 changed files with 82 additions and 0 deletions
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24
src/arch/x86/include/bootblock_common.h
View File

@ -34,3 +34,27 @@ static void sanitize_cmos(void)
}
}
#endif
#if CONFIG_CMOS_POST
#include <pc80/mc146818rtc.h>
static void cmos_post_init(void)
{
u8 magic = CMOS_POST_BANK_0_MAGIC;
/* Switch to the other bank */
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_1_MAGIC:
break;
case CMOS_POST_BANK_0_MAGIC:
magic = CMOS_POST_BANK_1_MAGIC;
break;
default:
/* Initialize to zero */
cmos_write(0, CMOS_POST_BANK_0_OFFSET);
cmos_write(0, CMOS_POST_BANK_1_OFFSET);
}
cmos_write(magic, CMOS_POST_BANK_OFFSET);
}
#endif