sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add support for storing POST codes in CMOS

Browse Source 
This will use 3 bytes of CMOS to keep track of the POST
code for the current boot while also leaving a record of
the previous boot.

The active bank is switched early in the bootblock.

Test:
1) clear cmos
2) reboot
3) use "mosys nvram dump" to verify that the first byte
contains 0x80 and the second byte contains 0xF8
4) powerd_suspend and then resume
5) use "mosys nvram dump" to verify that the first byte
contains 0x81 and the second byte contains 0xFD

Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie
2012-09-09 19:09:56 -07:00
committed by Stefan Reinauer
parent 31409617a4
commit b6e97b19ae
5 changed files with 82 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/console/post.c
View File

@ -21,6 +21,7 @@
#include <arch/io.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
/* Write POST information */
@ -38,6 +39,20 @@ void __attribute__((weak)) mainboard_post(uint8_t value)
#define mainboard_post(x)
#endif
#if CONFIG_CMOS_POST
static void cmos_post_code(u8 value)
{
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
cmos_write(value, CMOS_POST_BANK_0_OFFSET);
break;
case CMOS_POST_BANK_1_MAGIC:
cmos_write(value, CMOS_POST_BANK_1_OFFSET);
break;
}
}
#endif /* CONFIG_CMOS_POST */
void post_code(uint8_t value)
{
#if !CONFIG_NO_POST
@ -45,6 +60,9 @@ void post_code(uint8_t value)
print_emerg("POST: 0x");
print_emerg_hex8(value);
print_emerg("\n");
#endif
#if CONFIG_CMOS_POST
cmos_post_code(value);
#endif
outb(value, CONFIG_POST_PORT);
#endif