From b702ccb9637d2bfd66ca9f26fee57d28e2ff293d Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 15 Jan 2021 11:46:56 -0700 Subject: [PATCH] Fix compilation after merging upstream Change-Id: Ic2dbbf351f2b14b6d9a1c1b123ce2553a73a2f79 --- src/drivers/intel/gma/acpi/gfx.asl | 3 --- src/mainboard/system76/addw1/Kconfig | 2 +- src/mainboard/system76/addw1/devicetree.cb | 13 +-------- src/mainboard/system76/addw1/dsdt.asl | 10 ++++--- src/mainboard/system76/addw1/ramstage.c | 2 +- src/mainboard/system76/addw2/Kconfig | 2 +- src/mainboard/system76/addw2/devicetree.cb | 15 ++--------- src/mainboard/system76/addw2/dsdt.asl | 10 ++++--- src/mainboard/system76/addw2/ramstage.c | 2 +- src/mainboard/system76/bonw14/Kconfig | 10 +------ src/mainboard/system76/bonw14/devicetree.cb | 16 ++---------- src/mainboard/system76/bonw14/dsdt.asl | 10 ++++--- src/mainboard/system76/bonw14/ramstage.c | 2 +- src/mainboard/system76/cml-u/Kconfig | 2 +- src/mainboard/system76/cml-u/devicetree.cb | 13 +-------- src/mainboard/system76/cml-u/dsdt.asl | 4 +-- src/mainboard/system76/cml-u/ramstage.c | 3 +-- src/mainboard/system76/darp7/dsdt.asl | 29 +++++++-------------- src/mainboard/system76/galp5/dsdt.asl | 29 +++++++-------------- src/mainboard/system76/gaze15/Kconfig | 2 +- src/mainboard/system76/gaze15/devicetree.cb | 13 +-------- src/mainboard/system76/gaze15/dsdt.asl | 10 ++++--- src/mainboard/system76/gaze15/ramstage.c | 2 +- src/mainboard/system76/lemp10/dsdt.asl | 29 +++++++-------------- src/mainboard/system76/lemp9/devicetree.cb | 3 --- src/mainboard/system76/oryp5/devicetree.cb | 13 +-------- src/mainboard/system76/oryp5/dsdt.asl | 6 ++--- src/mainboard/system76/oryp5/ramstage.c | 3 +-- src/mainboard/system76/oryp6/Kconfig | 2 +- src/mainboard/system76/oryp6/devicetree.cb | 13 +-------- src/mainboard/system76/oryp6/dsdt.asl | 10 ++++--- src/mainboard/system76/oryp6/ramstage.c | 2 +- src/mainboard/system76/whl-u/devicetree.cb | 15 ++--------- src/mainboard/system76/whl-u/dsdt.asl | 4 +-- src/mainboard/system76/whl-u/ramstage.c | 3 +-- src/soc/intel/tigerlake/fsp_params.c | 2 +- 36 files changed, 93 insertions(+), 216 deletions(-) diff --git a/src/drivers/intel/gma/acpi/gfx.asl b/src/drivers/intel/gma/acpi/gfx.asl index 586408bf97..109543fd6f 100644 --- a/src/drivers/intel/gma/acpi/gfx.asl +++ b/src/drivers/intel/gma/acpi/gfx.asl @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Hack for including GMA ACPI code -#ifndef SYSTEM76_ACPI_NO_GFX0 Device (GFX0) { Name (_ADR, 0x00020000) } -#endif // SYSTEM76_ACPI_NO_GFX0 diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index d83b168331..1af06a5bf5 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -13,9 +13,9 @@ config BOARD_SPECIFIC_OPTIONS select EC_SYSTEM76_EC_OLED select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select HAVE_SMI_HANDLER select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 0cbf653e61..8889ad76f1 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/cannonlake # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 90, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -60,7 +54,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" # HDD (SATA0B) @@ -94,9 +88,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C @@ -181,8 +172,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/addw1/dsdt.asl b/src/mainboard/system76/addw1/dsdt.asl index ccbe190caf..7555246700 100644 --- a/src/mainboard/system76/addw1/dsdt.asl +++ b/src/mainboard/system76/addw1/dsdt.asl @@ -4,24 +4,26 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include - Device (\_SB.PCI0) { + Device (\_SB.PCI0) + { #include #include } #include - Scope (\_SB.PCI0.LPCB) { + Scope (\_SB.PCI0.LPCB) + { #include } diff --git a/src/mainboard/system76/addw1/ramstage.c b/src/mainboard/system76/addw1/ramstage.c index f4b1839a4b..ca72aae60d 100644 --- a/src/mainboard/system76/addw1/ramstage.c +++ b/src/mainboard/system76/addw1/ramstage.c @@ -3,7 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) { +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/addw2/Kconfig b/src/mainboard/system76/addw2/Kconfig index 6590caecce..84ccb86720 100644 --- a/src/mainboard/system76/addw2/Kconfig +++ b/src/mainboard/system76/addw2/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS select NO_UART_ON_SUPERIO select PCIEXP_HOTPLUG select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD diff --git a/src/mainboard/system76/addw2/devicetree.cb b/src/mainboard/system76/addw2/devicetree.cb index 345d6ecdb3..118d1be578 100644 --- a/src/mainboard/system76/addw2/devicetree.cb +++ b/src/mainboard/system76/addw2/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/cannonlake # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 90, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -60,7 +54,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" # HDD (SATA0B) @@ -94,9 +88,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C @@ -127,7 +118,7 @@ chip soc/intel/cannonlake register "usb3_ports[8]" = "USB3_PORT_EMPTY" register "usb3_ports[9]" = "USB3_PORT_EMPTY" - # PCI Express Graphics #0 x16, Clock (NVIDIA GPU) + # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" # PCI Express root port #9 x4, Clock 9 (SSD1) @@ -181,8 +172,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/addw2/dsdt.asl b/src/mainboard/system76/addw2/dsdt.asl index ccbe190caf..7555246700 100644 --- a/src/mainboard/system76/addw2/dsdt.asl +++ b/src/mainboard/system76/addw2/dsdt.asl @@ -4,24 +4,26 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include - Device (\_SB.PCI0) { + Device (\_SB.PCI0) + { #include #include } #include - Scope (\_SB.PCI0.LPCB) { + Scope (\_SB.PCI0.LPCB) + { #include } diff --git a/src/mainboard/system76/addw2/ramstage.c b/src/mainboard/system76/addw2/ramstage.c index f4b1839a4b..ca72aae60d 100644 --- a/src/mainboard/system76/addw2/ramstage.c +++ b/src/mainboard/system76/addw2/ramstage.c @@ -3,7 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) { +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig index c0f419592b..26d724c1ab 100644 --- a/src/mainboard/system76/bonw14/Kconfig +++ b/src/mainboard/system76/bonw14/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select NO_UART_ON_SUPERIO select PCIEXP_HOTPLUG select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_S select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD @@ -27,14 +27,6 @@ config BOARD_SPECIFIC_OPTIONS select TPM_RDRESP_NEED_DELAY select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB -# Hack for correct FSP headers until coreboot is updated -config FSP_HEADER_PATH - default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" - -# Hack for correct FSP blobs until coreboot is updated -config FSP_FD_PATH - default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/FSP.fd" - config MAINBOARD_DIR string default "system76/bonw14" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index 2447d36762..161f11003a 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -14,12 +14,9 @@ chip soc/intel/cannonlake register "SendVrMbxCmd" = "2" # ACPI (soc/intel/cannonlake/acpi.c) - # Enable s0ix + # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 160, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -49,7 +43,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" @@ -83,9 +77,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1 @@ -180,13 +171,10 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" - # TODO: painfully verify this shit # Power # sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10 # WARNING: must then be mapped from FSP value to PCH value diff --git a/src/mainboard/system76/bonw14/dsdt.asl b/src/mainboard/system76/bonw14/dsdt.asl index ccbe190caf..7555246700 100644 --- a/src/mainboard/system76/bonw14/dsdt.asl +++ b/src/mainboard/system76/bonw14/dsdt.asl @@ -4,24 +4,26 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include - Device (\_SB.PCI0) { + Device (\_SB.PCI0) + { #include #include } #include - Scope (\_SB.PCI0.LPCB) { + Scope (\_SB.PCI0.LPCB) + { #include } diff --git a/src/mainboard/system76/bonw14/ramstage.c b/src/mainboard/system76/bonw14/ramstage.c index f4b1839a4b..ca72aae60d 100644 --- a/src/mainboard/system76/bonw14/ramstage.c +++ b/src/mainboard/system76/bonw14/ramstage.c @@ -3,7 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) { +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig index d49dfd3514..c7421bcba3 100644 --- a/src/mainboard/system76/cml-u/Kconfig +++ b/src/mainboard/system76/cml-u/Kconfig @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS select NO_UART_ON_SUPERIO select PCIEXP_HOTPLUG select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 1de26928fa..b84af05f0c 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -16,9 +16,6 @@ chip soc/intel/cannonlake # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -29,9 +26,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -47,7 +41,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" @@ -81,9 +75,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE @@ -141,8 +132,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/cml-u/dsdt.asl b/src/mainboard/system76/cml-u/dsdt.asl index eac27b56f1..7555246700 100644 --- a/src/mainboard/system76/cml-u/dsdt.asl +++ b/src/mainboard/system76/cml-u/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include diff --git a/src/mainboard/system76/cml-u/ramstage.c b/src/mainboard/system76/cml-u/ramstage.c index 4b0ddd4823..ca72aae60d 100644 --- a/src/mainboard/system76/cml-u/ramstage.c +++ b/src/mainboard/system76/cml-u/ramstage.c @@ -3,8 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/darp7/dsdt.asl b/src/mainboard/system76/darp7/dsdt.asl index e77f70bd65..09b20de5df 100644 --- a/src/mainboard/system76/darp7/dsdt.asl +++ b/src/mainboard/system76/darp7/dsdt.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//TODO: cleaner solution for ACPI brightness -#define SYSTEM76_ACPI_NO_GFX0 - #include - DefinitionBlock( "dsdt.aml", "DSDT", @@ -15,27 +11,22 @@ DefinitionBlock( ) { #include - - // global NVS and variables #include - - // CPU #include - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } - } - - Scope (\_SB.PCI0.LPCB) { - #include + Device (\_SB.PCI0) + { + #include + #include + #include } #include + Scope (\_SB.PCI0.LPCB) + { + #include + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/system76/galp5/dsdt.asl b/src/mainboard/system76/galp5/dsdt.asl index e77f70bd65..09b20de5df 100644 --- a/src/mainboard/system76/galp5/dsdt.asl +++ b/src/mainboard/system76/galp5/dsdt.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//TODO: cleaner solution for ACPI brightness -#define SYSTEM76_ACPI_NO_GFX0 - #include - DefinitionBlock( "dsdt.aml", "DSDT", @@ -15,27 +11,22 @@ DefinitionBlock( ) { #include - - // global NVS and variables #include - - // CPU #include - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } - } - - Scope (\_SB.PCI0.LPCB) { - #include + Device (\_SB.PCI0) + { + #include + #include + #include } #include + Scope (\_SB.PCI0.LPCB) + { + #include + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index c4bb28bfa9..52007967ec 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5c7fdbb406..f00c6b646d 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -14,12 +14,9 @@ chip soc/intel/cannonlake register "SendVrMbxCmd" = "2" # ACPI (soc/intel/cannonlake/acpi.c) - # Enable s0ix + # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 90, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -94,9 +88,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left @@ -170,8 +161,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/gaze15/dsdt.asl b/src/mainboard/system76/gaze15/dsdt.asl index ccbe190caf..7555246700 100644 --- a/src/mainboard/system76/gaze15/dsdt.asl +++ b/src/mainboard/system76/gaze15/dsdt.asl @@ -4,24 +4,26 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include - Device (\_SB.PCI0) { + Device (\_SB.PCI0) + { #include #include } #include - Scope (\_SB.PCI0.LPCB) { + Scope (\_SB.PCI0.LPCB) + { #include } diff --git a/src/mainboard/system76/gaze15/ramstage.c b/src/mainboard/system76/gaze15/ramstage.c index f4b1839a4b..ca72aae60d 100644 --- a/src/mainboard/system76/gaze15/ramstage.c +++ b/src/mainboard/system76/gaze15/ramstage.c @@ -3,7 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) { +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/lemp10/dsdt.asl b/src/mainboard/system76/lemp10/dsdt.asl index e77f70bd65..09b20de5df 100644 --- a/src/mainboard/system76/lemp10/dsdt.asl +++ b/src/mainboard/system76/lemp10/dsdt.asl @@ -1,10 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//TODO: cleaner solution for ACPI brightness -#define SYSTEM76_ACPI_NO_GFX0 - #include - DefinitionBlock( "dsdt.aml", "DSDT", @@ -15,27 +11,22 @@ DefinitionBlock( ) { #include - - // global NVS and variables #include - - // CPU #include - Scope (\_SB) { - Device (PCI0) - { - #include - #include - #include - } - } - - Scope (\_SB.PCI0.LPCB) { - #include + Device (\_SB.PCI0) + { + #include + #include + #include } #include + Scope (\_SB.PCI0.LPCB) + { + #include + } + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 28cc9b18b0..83a03adb71 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -19,9 +19,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 6d3a77c4d5..ff2da4ee2e 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/cannonlake # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 78, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -60,7 +54,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" @@ -81,9 +75,6 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[6]" = "0" register "SataPortsDevSlp[7]" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP @@ -162,8 +153,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/oryp5/dsdt.asl b/src/mainboard/system76/oryp5/dsdt.asl index 9b1aa40c6f..7555246700 100644 --- a/src/mainboard/system76/oryp5/dsdt.asl +++ b/src/mainboard/system76/oryp5/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, /* DSDT revision: ACPI 2.0 and up */ + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 /* OEM revision */ + 0x20110725 // OEM revision ) { - #include + #include #include #include diff --git a/src/mainboard/system76/oryp5/ramstage.c b/src/mainboard/system76/oryp5/ramstage.c index 4b0ddd4823..ca72aae60d 100644 --- a/src/mainboard/system76/oryp5/ramstage.c +++ b/src/mainboard/system76/oryp5/ramstage.c @@ -3,8 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index 6754fbc58a..95f722d6b8 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select NO_UART_ON_SUPERIO select PCIEXP_HOTPLUG select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index e62b4eb724..64cf65899c 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -17,9 +17,6 @@ chip soc/intel/cannonlake # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -32,9 +29,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 90, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -60,7 +54,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" @@ -94,9 +88,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C @@ -181,8 +172,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/oryp6/dsdt.asl b/src/mainboard/system76/oryp6/dsdt.asl index ccbe190caf..7555246700 100644 --- a/src/mainboard/system76/oryp6/dsdt.asl +++ b/src/mainboard/system76/oryp6/dsdt.asl @@ -4,24 +4,26 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include - Device (\_SB.PCI0) { + Device (\_SB.PCI0) + { #include #include } #include - Scope (\_SB.PCI0.LPCB) { + Scope (\_SB.PCI0.LPCB) + { #include } diff --git a/src/mainboard/system76/oryp6/ramstage.c b/src/mainboard/system76/oryp6/ramstage.c index f4b1839a4b..ca72aae60d 100644 --- a/src/mainboard/system76/oryp6/ramstage.c +++ b/src/mainboard/system76/oryp6/ramstage.c @@ -3,7 +3,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) { +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index e241a967bc..581afd289a 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -13,12 +13,9 @@ chip soc/intel/cannonlake register "SendVrMbxCmd" = "2" # ACPI (soc/intel/cannonlake/acpi.c) - # Enable s0ix + # Disable s0ix register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" - # Disable DPTF register "dptf_enable" = "0" @@ -29,9 +26,6 @@ chip soc/intel/cannonlake .tdp_pl2_override = 30, }" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" @@ -57,7 +51,7 @@ chip soc/intel/cannonlake }" # SATA - register "SataMode" = "Sata_AHCI" + register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" @@ -91,9 +85,6 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSndw3" = "0" register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" - # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE @@ -151,8 +142,6 @@ chip soc/intel/cannonlake # Misc register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "Heci3Enabled" = "0" register "AcousticNoiseMitigation" = "1" #register "dmipwroptimize" = "1" #register "satapwroptimize" = "1" diff --git a/src/mainboard/system76/whl-u/dsdt.asl b/src/mainboard/system76/whl-u/dsdt.asl index eac27b56f1..7555246700 100644 --- a/src/mainboard/system76/whl-u/dsdt.asl +++ b/src/mainboard/system76/whl-u/dsdt.asl @@ -4,13 +4,13 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision ) { - #include + #include #include #include diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c index a3c4ffe5a0..72b680724a 100644 --- a/src/mainboard/system76/whl-u/ramstage.c +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -11,8 +11,7 @@ #include #include "gpio.h" -void mainboard_silicon_init_params(FSP_S_CONFIG *params) -{ +void mainboard_silicon_init_params(FSPS_UPD *supd) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 54bb19e08b..46ce366471 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -136,7 +136,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ITbtConnectTopologyTimeoutInMs = 0; /* Disable TcColdOnUsbConnect */ - params->DisableTccoldOnUsbConnected = 1; + //TODO params->DisableTccoldOnUsbConnected = 1; /* Chipset Lockdown */ if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {