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arch/x86: Clean up PIRQ_ROUTE

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This code is currently only used by via/epia-m850,
it is also somewhat buggy.

Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-07-04 21:08:17 +03:00
parent 3a2660e489
commit b72b5d9528
3 changed files with 21 additions and 22 deletions
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15
src/Kconfig
View File

@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE
file containing NVRAM/CMOS bit definitions. file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig. It defaults to 'n' but can be selected in mainboard/*/Kconfig.
config PIRQ_ROUTE
bool
default n
config HAVE_SMI_HANDLER config HAVE_SMI_HANDLER
bool bool
default n default n
@ -591,17 +587,6 @@ config HAVE_PIRQ_TABLE
Whether or not the PIRQ table is actually generated by coreboot Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE. is configurable by the user via GENERATE_PIRQ_TABLE.
config MAX_PIRQ_LINKS
int
default 4
help
This variable specifies the number of PIRQ interrupt links which are
routable. On most chipsets, this is 4, INTA through INTD. Some
chipsets offer more than four links, commonly up to INTH. They may
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
table specifies links greater than 4, pirq_route_irqs will not
function properly, unless this variable is correctly set.
config COMMON_FADT config COMMON_FADT
bool bool
default n default n

16
src/arch/x86/Kconfig
View File

@ -329,3 +329,19 @@ config HAVE_CF9_RESET
config HAVE_CF9_RESET_PREPARE config HAVE_CF9_RESET_PREPARE
bool bool
depends on HAVE_CF9_RESET depends on HAVE_CF9_RESET
config PIRQ_ROUTE
bool
default n
config MAX_PIRQ_LINKS
int
default 4
depends on PIRQ_ROUTE
help
This variable specifies the number of PIRQ interrupt links which are
routable. On most chipsets, this is 4, INTA through INTD. Some
chipsets offer more than four links, commonly up to INTH. They may
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
table specifies links greater than 4, pirq_route_irqs will not
function properly, unless this variable is correctly set.

12
src/arch/x86/pirq_routing.c
View File

@ -20,10 +20,6 @@
#include <string.h> #include <string.h>
#include <device/pci.h> #include <device/pci.h>
void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
{
}
static void check_pirq_routing_table(struct irq_routing_table *rt) static void check_pirq_routing_table(struct irq_routing_table *rt)
{ {
uint8_t *addr = (uint8_t *)rt; uint8_t *addr = (uint8_t *)rt;
@ -146,8 +142,11 @@ static void pirq_route_irqs(unsigned long addr)
/* Set PCI IRQs. */ /* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) { for (i = 0; i < num_entries; i++) {
u8 bus = pirq_tbl->slots[i].bus;
u8 devfn = pirq_tbl->slots[i].devfn;
printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot); devfn >> 3, pirq_tbl->slots[i].slot);
for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) {
@ -178,8 +177,7 @@ static void pirq_route_irqs(unsigned long addr)
} }
/* Bus, device, slots IRQs for {A,B,C,D}. */ /* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus, pci_assign_irqs(bus, devfn >> 3, irq_slot);
pirq_tbl->slots[i].devfn >> 3, irq_slot);
} }
for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++)