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nb/intel/sandybridge/raminit: Add tCPDED corner case

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tCPDED is always 1, except for steppings earlier than Sandy Bridge D0.
Reduces the differences to MRC.bin.

Tested on Lenovo X220: Still boots and runs fine.

Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Patrick Rudolph
2023-12-21 14:53:45 +01:00
committed by Felix Held
parent 220bd26b6e
commit b7341da191
1 changed files with 5 additions and 2 deletions
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5
src/northbridge/intel/sandybridge/raminit_common.c
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@@ -171,7 +171,7 @@ void dram_timing_regs(ramctr_timing *ctrl)
.tXPDLL = MIN(ctrl->tXPDLL, 31), .tXPDLL = MIN(ctrl->tXPDLL, 31),
.tXP = MIN(ctrl->tXP, 7), .tXP = MIN(ctrl->tXP, 7),
.tAONPD = ctrl->tAONPD, .tAONPD = ctrl->tAONPD,
.tCPDED = 2, .tCPDED = 1,
.tPRPDEN = 1, .tPRPDEN = 1,
}; };
@@ -2816,6 +2816,9 @@ void final_registers(ramctr_timing *ctrl)
union tc_othp_reg tc_othp = { union tc_othp_reg tc_othp = {
.raw = mchbar_read32(TC_OTHP_ch(channel)), .raw = mchbar_read32(TC_OTHP_ch(channel)),
}; };
if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) < SNB_STEP_D0)
tc_othp.tCPDED = 2;
else
tc_othp.tCPDED = 1; tc_othp.tCPDED = 1;
mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw);