mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbi
copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This commit is contained in:
Sheng-Liang Pan
committed by
Eric Lai
Eric Lai
parent
cbbdaf4524
commit
b766b16a57
@@ -205,6 +205,9 @@ config BOARD_GOOGLE_SHOTZO
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config BOARD_GOOGLE_TARANZA
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bool "-> Taranza"
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select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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config BOARD_GOOGLE_BOXY
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bool "-> Boxy"
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@@ -0,0 +1,3 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-y += gpio.c
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93
src/mainboard/google/dedede/variants/taranza/gpio.c
Normal file
93
src/mainboard/google/dedede/variants/taranza/gpio.c
Normal file
@@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A11 : TOUCH_RPT_EN */
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PAD_NC(GPP_A11, NONE),
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/* A12 : USB_OC1_N */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : USB_OC2_N */
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* A14 : USB_OC3_N */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A18 : USB_OC0_N */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* B9 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* D2 : PWM_PP3300_BUZZER */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D4 : LAN_PE_ISOLATE_ODL_R */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : TOUCH_RESET_L */
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PAD_NC(GPP_D5, NONE),
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/* D6 : EN_PP3300_TOUCH_S0 */
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PAD_NC(GPP_D6, NONE),
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/* D17 : LAN_PERST_L */
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PAD_CFG_GPO(GPP_D17, 1, PLTRST),
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/* D19 : WWAN_WLAN_COEX1 */
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PAD_NC(GPP_D19, NONE),
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/* D20 : WWAN_WLAN_COEX2 */
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PAD_NC(GPP_D20, NONE),
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/* E13 : GPP_E13/DDI0_DDC_SCL */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* E14 : GPP_E14/DDI0_DDC_SDA */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : GPP_E15/DDI1_DDC_SCL */
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PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
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/* E16 : GPP_E16/DDI1_DDC_SDA */
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PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
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/* G0 : SD_CMD */
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PAD_NC(GPP_G0, NONE),
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/* G1 : SD_DATA0 */
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PAD_NC(GPP_G1, NONE),
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/* G2 : SD_DATA1 */
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PAD_NC(GPP_G2, NONE),
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/* G3 : SD_DATA2 */
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PAD_NC(GPP_G3, NONE),
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/* G4 : SD_DATA3 */
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PAD_NC(GPP_G4, NONE),
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/* G5 : SD_CD_ODL */
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PAD_NC(GPP_G5, NONE),
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/* G6 : SD_CLK */
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PAD_NC(GPP_G6, NONE),
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/* G7 : SD_SDIO_WP */
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PAD_NC(GPP_G7, NONE),
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/* H4 : AP_I2C_TS_SDA */
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PAD_NC(GPP_H4, NONE),
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/* H5 : AP_I2C_TS_SCL */
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PAD_NC(GPP_H5, NONE),
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/* H6 : AP_I2C_CAM_SDA */
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PAD_NC(GPP_H6, NONE),
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/* H7 : AP_I2C_CAM_SCL */
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PAD_NC(GPP_H7, NONE),
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/* H15 : I2S_SPK_BCLK */
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PAD_NC(GPP_H15, NONE),
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/* R6 : I2S_SPK_LRCK */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S_SPK_AUDIO */
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PAD_NC(GPP_R7, NONE),
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/* S2 : DMIC1_CLK */
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PAD_NC(GPP_S2, NONE),
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/* S3 : DMIC1_DATA */
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PAD_NC(GPP_S3, NONE),
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/* S6 : DMIC0_CLK */
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PAD_NC(GPP_S6, NONE),
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/* S7 : DMIC0_DATA */
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PAD_NC(GPP_S7, NONE),
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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@@ -8,10 +8,6 @@ chip soc/intel/jasperlake
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | Trackpad |
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#| I2C1 | Digitizer |
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#| I2C2 | Touchscreen |
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#| I2C3 | Camera |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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@@ -19,24 +15,245 @@ chip soc/intel/jasperlake
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 190,
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.scl_hcnt = 100,
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.sda_hold = 40,
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}
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},
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}"
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# Enable Root Port 3 (index 2) for LAN
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# External PCIe port 7 is mapped to PCIe Root Port 3
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register "PcieRpEnable[2]" = "1"
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register "PcieClkSrcUsage[4]" = "2"
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# Enable Root Port 7 (index 6) for WLAN
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# External PCIe port 3 is mapped to PCIe Root Port 7
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[3]" = "6"
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# Disable PCIe Root Port 8
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register "PcieRpEnable[7]" = "0"
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# Audio related configurations
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register "PchHdaAudioLinkDmicEnable[0]" = "0"
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register "PchHdaAudioLinkDmicEnable[1]" = "0"
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# Disable SD card
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register "sdcard_cd_gpio" = "0"
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register "SdCardPowerEnableActiveHigh" = "0"
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# Disable eDP on port A
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register "DdiPortAConfig" = "0"
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# Enable HPD and DDC for DDI port A
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "1"
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# USB Port Configuration
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-C Port 0
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register "usb2_ports[1]" = "{
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.enable = 1,
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.ocpin = OC1,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A0
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register "usb2_ports[2]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A1
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register "usb2_ports[3]" = "{
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.enable = 1,
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.ocpin = OC3,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A2
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register "usb2_ports[4]" = "{
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.enable = 1,
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.ocpin = OC0,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A3
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # PL2303
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register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
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device domain 0 on
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device pci 15.0 on end
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device pci 04.0 on
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chip drivers/intel/dptf
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 100,
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},
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.pl2 = {
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.min_power = 20000,
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.max_power = 20000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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register "options.tsr[0].desc" = ""Memory""
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register "options.tsr[1].desc" = ""Power""
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register "options.tsr[2].desc" = ""Chassis""
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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device generic 0 on end
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end
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end # SA Thermal device
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device pci 14.0 on
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chip drivers/usb/acpi
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# TODO (b/264960828) verify PLD values
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device usb 0.0 on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device usb 2.0 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device usb 2.1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 3)"
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device usb 2.2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A2""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 4)"
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device usb 2.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A3""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 5)"
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device usb 2.4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device usb 3.0 on end
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end
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chip drivers/usb/acpi
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device usb 3.1 off end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device usb 3.2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 3)"
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device usb 3.3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A2""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 4)"
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device usb 3.4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A3""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 5)"
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device usb 3.5 on end
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end
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end
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end
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end # USB xHCI
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device pci 15.0 off end # I2C 0
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device pci 15.1 off end # I2C 1
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device pci 15.2 off end # I2C 2
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device pci 15.3 off end # I2C 3
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device pci 19.0 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end # I2C 4
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device pci 1c.2 on
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chip drivers/net
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register "customized_leds" = "0x05af"
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register "wake" = "GPE0_DW0_03" # GPP_B3
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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register "device_index" = "0"
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device pci 00.0 on end
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end
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end # PCI Express Root Port 3 - RTL8111H LAN
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device pci 1c.6 on
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW2_03"
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device pci 00.0 on end
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end
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end # PCI Express Root Port 7 - WLAN
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device pci 1c.7 off end # PCI Express Root Port 8
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device pci 1f.3 on end # Intel HDA
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end
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end
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