intel/littleplains: Update with recent changes to mohonpeak

- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
- Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
- Remove fixed microcode location.

Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12635
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>

src/mainboard/intel/littleplains/Kconfig

@@ -58,16 +58,12 @@ config UART_FOR_CONSOLE
 	help
 	  The Little Plains board uses COM2 (2f8) for the serial console.
 
-config SEABIOS_MALLOC_UPPERMEMORY
+config PAYLOAD_CONFIGFILE
-	bool
+	string
-	default n
+	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
 	help
 	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 	  we put the SeaBIOS buffer area down in the 0x9000 segment.
 
-config CPU_MICROCODE_CBFS_LOC
-	hex
-	default 0xfff60040
-
 endif # BOARD_INTEL_LITTLEPLAINS

src/mainboard/intel/littleplains/config_seabios

@@ -0,0 +1,5 @@
+#  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+#  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+#  we put the SeaBIOS buffer area down in the 0x9000 segment.
+
+# CONFIG_MALLOC_UPPERMEMORY is not set