vendorcode/amd/agesa/fam16kb: Fix improper use of .data

AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.

TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.

Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/hp/abm/buildOpts.c

@@ -43,7 +43,7 @@
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 
-GPIO_CONTROL hp_abm_gpio[] = {
+CONST GPIO_CONTROL hp_abm_gpio[] = {
 	{ 45, Function2, GpioOutEnB | Sticky },                   // Signal input  APU_SD_LED
 	{ 49, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_UID
 	{ 50, Function2, PullUpB | PullDown | Sticky },           // Signal output APU_ABM_LED_HEALTH

src/northbridge/amd/agesa/family16kb/Kconfig

@@ -24,4 +24,7 @@ config VGA_BIOS_ID
 	  The default VGA BIOS PCI vendor/device ID should be set to the
 	  result of the map_oprom_vendev() function in northbridge.c.
 
+config AGESA_BROKEN_DATA_SECTION
+	default n
+
 endif # NORTHBRIDGE_AMD_AGESA_FAMILY16_KB

src/vendorcode/amd/agesa/f16kb/AGESA.h

@@ -2892,7 +2892,7 @@ typedef struct {
   IN SD_CLOCK_CONTROL CfgFchSdClockControl;       ///< FCH SD Clock Control
   IN SCI_MAP_CONTROL  *CfgFchSciMapControl;       ///< FCH SCI Mapping Control
   IN SATA_PHY_CONTROL *CfgFchSataPhyControl;      ///< FCH SATA PHY Control
-  IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
+  CONST IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
   IN BOOLEAN           CfgFchRtcWorkAround;       ///< FCH RTC Workaround
 } FCH_PLATFORM_POLICY;
 
@@ -3032,7 +3032,7 @@ typedef struct {
                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
   IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
                                                   ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
-  IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
+  CONST IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
 
   IN BOOLEAN    CfgIommuSupport;                  ///< IOMMU support
   IN UINT8      CfgLvdsPowerOnSeqDigonToDe;       ///< Panel initialization timing

src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h

@@ -59,7 +59,7 @@
 #include "OptionPrefetchModeInstall.h"
 #include "OptionPreserveMailboxInstall.h"
 
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] =
 {
   OPTION_MSG_BASED_C1E_FEAT
   OPTION_L3_FEAT

src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h

@@ -87,7 +87,7 @@
 
 
     #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F16KbRegisterTables[] =
+      CONST REGISTER_TABLE ROMDATA * CONST F16KbRegisterTables[] =
       {
         #if MODEL_SPECIFIC_PCI == TRUE
           &F16KbPciRegisterTableBeforeApLaunch,
@@ -223,7 +223,7 @@
         #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch,
       #endif
 
-      CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] =
+      CONST UINT8 ROMDATA * CONST CpuF16KbMicroCodePatchArray[] =
       {
         F16_KB_UCODE_7001
         F16_KB_UCODE_7000
@@ -253,7 +253,7 @@
 #if USES_REGISTER_TABLES == TRUE
   extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable;
   extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable;
-  CONST REGISTER_TABLE ROMDATA *F16UnknownRegisterTables[] =
+  CONST REGISTER_TABLE ROMDATA * CONST F16UnknownRegisterTables[] =
   {
     &F16PciUnknownRegisterTable,
     &F16MsrUnknownRegisterTable

src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h

@@ -832,7 +832,7 @@
       //
       // Define task list for InitReset phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitResetTaskTable[] = {
         InstallFchInitResetHwAcpiP,
         InstallFchInitResetAb,
         InstallFchInitResetSpi,
@@ -859,7 +859,7 @@
       //
       // Define task list for InitEnv phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitEnvTaskTable[] = {
         InstallFchInitEnvHwAcpiP,
         InstallFchInitEnvPcib,
         InstallFchInitEnvPcie,
@@ -892,7 +892,7 @@
       //
       // Define task list for InitMid phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitMidTaskTable[] = {
         InstallFchInitMidImc,
         InstallFchInitMidUsb,
         InstallFchInitMidUsbEhci,
@@ -913,7 +913,7 @@
       //
       // Define task list for InitLate phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitLateTaskTable[] = {
         InstallFchInitLatePcie,
         InstallFchInitLatePcib,
         InstallFchInitLateSpi,
@@ -940,7 +940,7 @@
       //
       // Define task list for S3 resume before PCI phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitS3EarlyTaskTable[] = {
         InstallFchInitEnvPcie,
         InstallFchInitEnvPcib,
         InstallFchInitEnvGpp,
@@ -967,7 +967,7 @@
       //
       // Define task list for S3 resume after PCI phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitS3LateTaskTable[] = {
         InstallFchInitLatePcie,
         InstallFchInitLatePcib,
         InstallFchInitLateSpi,
@@ -991,7 +991,7 @@
       };
     #endif
   #endif
-  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
+  FCH_TASK_ENTRY   * CONST FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
 
 
 #else   // FCH_SUPPORT == FALSE

src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h

@@ -91,7 +91,7 @@
   #if (GNB_TYPE_KB == TRUE)
     #include "GnbInitKBInstall.h"
   #endif
-  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
+  CONST GNB_SERVICE   * CONST ServiceTable = SERVICES_POINTER;
 
 //---------------------------------------------------------------------------------------------------
 // BUILD options
@@ -292,7 +292,7 @@
     #define CFG_UMA_STEERING             0
   #endif
 
-  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
+  CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
     CFG_IGFX_AS_PCIE_EP,
     CFG_LCLK_DEEP_SLEEP_EN,
     CFG_LCLK_DPM_EN,
@@ -389,7 +389,7 @@
       #define OPTION_PCIEEARLYINTERFACEKB_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
       OPTION_GNBEARLYINTERFACETN_ENTRY
       OPTION_GNBEARLYINTERFACEKB_ENTRY
       OPTION_PCIECONFIGURATIONMAP_ENTRY
@@ -433,7 +433,7 @@
     #endif
 
 
-    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
       OPTION_PCIECONFIGURATIONINIT_ENTRY
       OPTION_GNBEARLIERINTERFACETN_ENTRY
       OPTION_GNBEARLIERINTERFACEKB_ENTRY
@@ -522,7 +522,7 @@
     #endif
 
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
       OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
       OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
       OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
@@ -531,7 +531,7 @@
       {0, NULL, EndGnbTestPoints}
     };
 
-    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
       OPTION_GNBPOSTINTERFACETN_ENTRY
       OPTION_GNBPOSTINTERFACEKB_ENTRY
       OPTION_PCIEPOSTINTERFACETN_ENTRY
@@ -605,7 +605,7 @@
 
   //---------------------------------------------------------------------------------------------------
 
-    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
       OPTION_GNBENVINTERFACETN_ENTRY
       OPTION_GNBENVINTERFACEKB_ENTRY
       OPTION_PCIEENVINTERFACETN_ENTRY
@@ -747,7 +747,7 @@
       #define OPTION_GNBNBIOAPICINTERFACE_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
       OPTION_GFXCONFIGMIDINTERFACE_ENTRY
       OPTION_GFXMIDINTERFACETN_ENTRY
       OPTION_GFXMIDINTERFACEKB_ENTRY
@@ -797,7 +797,7 @@
 
       #if (GNB_TYPE_KB == TRUE)
         extern F_ALIB_GET PcieAlibGetBaseTableKB;
-        F_ALIB_GET  *AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
+        F_ALIB_GET  * CONST AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
         extern F_ALIB_UPDATE PcieAlibUpdateVoltageData;
         extern F_ALIB_UPDATE PcieAlibUpdatePcieData;
         #undef ALIB_CALL_TABLEV2
@@ -806,11 +806,11 @@
       #endif
 
 
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
         ALIB_CALL_TABLE
         NULL
       };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
         ALIB_CALL_TABLEV2
         NULL
       };
@@ -823,12 +823,12 @@
         #define OPTION_PCIEALIBV2FEATURE_ENTRY              {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature},
       #endif
     #else
-      F_ALIB_GET  *AlibGetBaseTable = NULL;
+      F_ALIB_GET  * CONST AlibGetBaseTable = NULL;
-      F_ALIB_GET  *AlibGetBaseTableV2 = NULL;
+      F_ALIB_GET  * CONST AlibGetBaseTableV2 = NULL;
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
         NULL
       };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
         NULL
       };
       #define OPTION_PCIEALIBFEATURE_ENTRY
@@ -855,7 +855,7 @@
       #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
       #if (GNB_TYPE_TN == TRUE)
         OPTION_PCIEALIBFEATURE_ENTRY
       #endif
@@ -880,7 +880,7 @@
       #define OPTION_GFXINITSVIEW_ENTRY
     #endif
 
-    OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
       OPTION_GFXINITSVIEW_ENTRY
       {0, NULL, EndGnbTestPoints}
     };

src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h

@@ -219,7 +219,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #endif
 
 
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
     MEM_MAIN_FLOW_CONTROL_PTR_TN
     MEM_MAIN_FLOW_CONTROL_PTR_KB
     NULL
@@ -478,7 +478,7 @@ BOOLEAN MemFS3DefConstructorRet (
     #endif
     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 
-    MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
+    CONST MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
       MEM_FEATURE_ONLINE_SPARE,
       MEM_FEATURE_BANK_INTERLEAVE,
@@ -572,7 +572,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 
-    MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
+    CONST MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
       MEM_FEATURE_ONLINE_SPARE,
       MEM_FEATURE_BANK_INTERLEAVE,
@@ -608,7 +608,7 @@ BOOLEAN MemFS3DefConstructorRet (
    * MAIN FEATURE BLOCK
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
     MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
     MEM_MAIN_FEATURE_TRAINING,
     MEM_MAIN_FEATURE_DIMM_EXCLUDE,
@@ -731,7 +731,7 @@ BOOLEAN MemFS3DefConstructorRet (
         #undef TECH_TRAIN_DQS_2D_DDR3
         #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
       #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
+      CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
         TECH_TRAIN_ENTER_HW_TRN_DDR3,
         TECH_TRAIN_SW_WL_DDR3,
@@ -871,7 +871,7 @@ BOOLEAN MemFS3DefConstructorRet (
         #undef TECH_TRAIN_DQS_2D_DDR3
         #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
       #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
+      CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
         TECH_TRAIN_ENTER_HW_TRN_DDR3,
         TECH_TRAIN_SW_WL_DDR3,
@@ -916,13 +916,13 @@ BOOLEAN MemFS3DefConstructorRet (
 
 
   #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+  CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
   };
 
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+  CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
@@ -933,7 +933,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
     NB_TRAIN_FLOW_DDR2,
     NB_TRAIN_FLOW_DDR3,
   };
@@ -943,7 +943,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
     MEM_TECH_CONSTRUCTOR_DDR2
     MEM_TECH_CONSTRUCTOR_DDR3
     NULL
@@ -968,7 +968,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *----------------------------------------------------------------------
    */
 
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
     NULL
   };
   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
@@ -981,7 +981,7 @@ BOOLEAN MemFS3DefConstructorRet (
    */
   #define MEM_PSC_FLOW_BLOCK_END NULL
   #define PSC_TBL_END NULL
-  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
+  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, CONST MEM_PSC_TABLE_BLOCK *)) memDefTrue
 
   #define PSC_TBL_TN_UDIMM3_S2D_FM2
   #define PSC_TBL_TN_SODIMM3_S2D_FS1
@@ -1143,7 +1143,7 @@ BOOLEAN MemFS3DefConstructorRet (
       #define PSC_TBL_TN_CS_TRI_FP2
     #endif
 
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = {
+    PSC_TBL_ENTRY* CONST  memPSCTblMaxFreqArrayTN[] = {
       PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
       PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
       PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
@@ -1156,36 +1156,36 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayTN[] = {
       PSC_TBL_TN_UDIMM3_DRAM_TERM
       PSC_TBL_TN_SODIMM3_DRAM_TERM
       PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayTN[] = {
       &TNOdtPatTblEnt,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblSAOArrayTN[] = {
       PSC_TBL_TN_SODIMM3_SAO
       PSC_TBL_TN_SODWN_SODIMM3_SAO
       PSC_TBL_TN_UDIMM3_SAO
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayTN[] = {
       &TNMR0WrTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0CLArrayTN[] = {
       &TNMR0CLTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblGenArrayTN[] = {
       &TNDdr3CKETriEnt,
       PSC_TBL_TN_CLK_DIS_FM2
       PSC_TBL_TN_ODT_TRI_FM2
@@ -1199,7 +1199,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblS2DArrayTN[] = {
       PSC_TBL_TN_UDIMM3_S2D_FM2
       PSC_TBL_TN_SODIMM3_S2D_FS1
       PSC_TBL_TN_SODIMM3_S2D_FP2
@@ -1207,7 +1207,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
+    CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN,
       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN,
       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN,
@@ -1232,7 +1232,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern MEM_PSC_FLOW MemPGetMR0WrCL;
     extern MEM_PSC_FLOW MemPGetS2D;
 
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
+    CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
       &memPSCTblBlockTN,
       MemPGetMaxFreqSupported,
       MemPGetRttNomWr,
@@ -1382,7 +1382,7 @@ BOOLEAN MemFS3DefConstructorRet (
       #define PSC_TBL_KB_CS_TRI_FT3
     #endif
 
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMaxFreqArrayKB[] = {
       // 4 layer tables block
       PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
@@ -1397,7 +1397,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayKB[] = {
       PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
       PSC_TBL_KB_SODIMM3_DRAM_TERM
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
@@ -1405,13 +1405,13 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayKB[] = {
       &KB1DOdtPatTblEnt,
       &KB2DOdtPatTblEnt,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblSAOArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblSAOArrayKB[] = {
       PSC_TBL_KB_SODIMM3_SAO
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
       PSC_TBL_KB_SODWN_SAO
@@ -1419,17 +1419,17 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayKB[] = {
       &KBMR0WrTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayKB[] = {
+    PSC_TBL_ENTRY* CONST  memPSCTblMR0CLArrayKB[] = {
       &KBMR0CLTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblGenArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblGenArrayKB[] = {
       &KBDdr3CKETriEnt,
       PSC_TBL_KB_CLK_DIS_FT3
       PSC_TBL_KB_ODT_TRI_FT3
@@ -1437,13 +1437,13 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblS2DArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblS2DArrayKB[] = {
       PSC_TBL_KB_UDIMM3_S2D_FT3
       PSC_TBL_KB_SODIMM3_S2D_FT3
       PSC_TBL_END
     };
 
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
+    CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayKB,
       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayKB,
       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayKB,
@@ -1468,7 +1468,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern MEM_PSC_FLOW MemPGetMR0WrCL;
     extern MEM_PSC_FLOW MemPGetS2D;
 
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
+    CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
       &memPSCTblBlockKB,
       MemPGetMaxFreqSupported,
       MemPGetRttNomWr,
@@ -1489,7 +1489,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #endif
 
 
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+  CONST MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
     MEM_PSC_FLOW_BLOCK_TN
     MEM_PSC_FLOW_BLOCK_KB
     MEM_PSC_FLOW_BLOCK_END
@@ -1510,7 +1510,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #else //#if (OPTION_LRDIMMS == FALSE)
     #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
   #endif
-  MEM_TECH_LRDIMM memLrdimmSupported = {
+  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
     MEM_TECH_LRDIMM_STRUCT_VERSION,
     MEM_TECH_FEATURE_LRDIMM_INIT
   };
@@ -1521,7 +1521,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
     NULL
   };
   /*---------------------------------------------------------------------------------------------------
@@ -1530,7 +1530,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
     NULL,
     NULL,
   };
@@ -1540,7 +1540,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
     NULL
   };
 
@@ -1550,13 +1550,13 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
+  CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
 
   /*---------------------------------------------------------------------------------------------------
    * DEFAULT MAIN FEATURE BLOCK
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
     0
   };
 
@@ -1581,18 +1581,18 @@ BOOLEAN MemFS3DefConstructorRet (
    *---------------------------------------------------------------------------------------------------
    */
   #if OPTION_DDR2
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+    CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
       0
     };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+    CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
       { 0 }
     };
   #endif
   #if OPTION_DDR3
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+    CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
       0
     };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+    CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
       { 0 }
     };
   #endif
@@ -1607,7 +1607,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *----------------------------------------------------------------------
    */
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
     NULL
   };
 
@@ -1616,11 +1616,11 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *----------------------------------------------------------------------
    */
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+  MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
     NULL
   };
 
-  MEM_TECH_LRDIMM memLrdimmSupported = {
+  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
     MEM_TECH_LRDIMM_STRUCT_VERSION,
     NULL
   };
@@ -1632,13 +1632,13 @@ BOOLEAN MemFS3DefConstructorRet (
  *
  *---------------------------------------------------------------------------------------------------
  */
-MEM_NB_SUPPORT memNBInstalled[] = {
+CONST MEM_NB_SUPPORT memNBInstalled[] = {
   MEM_NB_SUPPORT_TN
   MEM_NB_SUPPORT_KB
   MEM_NB_SUPPORT_END
 };
 
-UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
+CONST UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
 
 
 #endif  // _OPTION_MEMORY_INSTALL_H_

src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h

@@ -89,7 +89,7 @@
 #endif
 
 /*  Declare the instance of the multisocket option configuration structure  */
-OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
+CONST OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
   MULTISOCKET_STRUCT_VERSION,
   GET_NUM_PM_STEPS,
   CORE0_PM_TASK,

src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h

@@ -48,7 +48,7 @@
  *
  ****************************************************************************/
 
-VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+CONST  AMD_MODULE_HEADER mCpuModuleID = {
   //ModuleHeaderSignature
   // Remove 'DOM$' as temp solution before update BinUtil.exe ,
   Int32FromChar ('0', '0', '0', '0'),
@@ -1706,7 +1706,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
  *
  ****************************************************************************/
 
-FCH_PLATFORM_POLICY  FchUserOptions = {
+CONST FCH_PLATFORM_POLICY  FchUserOptions = {
   CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
   CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
   CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
@@ -1754,7 +1754,7 @@ FCH_PLATFORM_POLICY  FchUserOptions = {
   CFG_FCH_RTC_WORKAROUND                // CfgFchRtcWorkaround
 };
 
-BUILD_OPT_CFG UserOptions = {
+CONST BUILD_OPT_CFG UserOptions = {
   {                                             // AGESA version string
     AGESA_CODE_SIGNATURE,                       //    code header Signature
     AGESA_PACKAGE_STRING,                       //    16 character ID
@@ -2130,4 +2130,3 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
 #if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
   CONST INT32 _fltused = 0;
 #endif
-

src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h

@@ -127,7 +127,7 @@ typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
 typedef BOOLEAN MEM_NB_CONSTRUCTOR (
   IN OUT   MEM_NB_BLOCK *NBPtr,
   IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  CONST IN       MEM_FEAT_BLOCK_NB *FeatPtr,
   IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
   IN       UINT8 NodeID
   );
@@ -250,7 +250,7 @@ typedef struct _MEM_NB_SUPPORT {
   UINT16              MemNBSupportVersion; ///< Version of northbridge support.
   MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
   MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
-  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
+  CONST MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
   MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
   MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
 } MEM_NB_SUPPORT;
@@ -270,7 +270,7 @@ typedef struct _MEM_FEAT_TRAIN_SEQ {
   UINT16              OptMemTrainingSequenceListVersion; ///< Version of main feature block.
   OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
   OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
-  MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
+  CONST MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
 } MEM_FEAT_TRAIN_SEQ;
 
 /**
@@ -297,7 +297,7 @@ typedef struct _MEM_PSC_TABLE_BLOCK {
 
 typedef BOOLEAN MEM_PSC_FLOW (
   IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  CONST IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
   );
 
 /**
@@ -305,7 +305,7 @@ typedef BOOLEAN MEM_PSC_FLOW (
  * specific configuration.
  */
 typedef struct _MEM_PSC_FLOW_BLOCK {
-  MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
+  CONST MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
   MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
   MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
   MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.

src/vendorcode/amd/agesa/f16kb/Proc/CPU/S3.h

@@ -265,24 +265,24 @@ typedef struct {
 typedef struct {
   UINT16                  Version;       ///< Version of header
   UINT16                  NumRegisters;  ///< Number of registers in the list
-  PCI_REG_DESCRIPTOR      *RegisterList; ///< Pointer to the first register descriptor
+  CONST PCI_REG_DESCRIPTOR      *RegisterList; ///< Pointer to the first register descriptor
-  PCI_SPECIAL_CASE        *SpecialCases; ///< Pointer to array of special case handlers
+  CONST PCI_SPECIAL_CASE        *SpecialCases; ///< Pointer to array of special case handlers
 } PCI_REGISTER_BLOCK_HEADER;
 
 /// S3 'conditional' PCI register list header.
 typedef struct {
   UINT16                          Version;       ///< Version of header
   UINT16                          NumRegisters;  ///< Number of registers in the list
-  CONDITIONAL_PCI_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
+  CONST CONDITIONAL_PCI_REG_DESCRIPTOR  *RegisterList; ///< Pointer to the first register descriptor
-  PCI_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
+  CONST PCI_SPECIAL_CASE                *SpecialCases; ///< Pointer to array of special case handlers
 } CPCI_REGISTER_BLOCK_HEADER;
 
 /// S3 MSR register list header.
 typedef struct {
   UINT16                 Version;       ///< Version of header
   UINT16                 NumRegisters;  ///< Number of registers in the list
-  MSR_REG_DESCRIPTOR     *RegisterList; ///< Pointer to the first register descriptor
+  CONST MSR_REG_DESCRIPTOR     *RegisterList; ///< Pointer to the first register descriptor
-  MSR_SPECIAL_CASE       *SpecialCases; ///< Pointer to array of special case handlers
+  CONST MSR_SPECIAL_CASE       *SpecialCases; ///< Pointer to array of special case handlers
 } MSR_REGISTER_BLOCK_HEADER;
 
 /// S3 'conditional' MSR register list header.

src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitEarly.c

@@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC)
  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  *----------------------------------------------------------------------------------------
  */
-EXECUTION_CACHE_REGION InitExeCacheMap[] =
+CONST EXECUTION_CACHE_REGION InitExeCacheMap[] =
 {
   {0x00000000, 0x00000000},
   {0x00000000, 0x00000000},

src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h

@@ -52,12 +52,12 @@ VOID          ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
 VOID          WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
 VOID          RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
 VOID          ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
-VOID          WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID          WritePci (IN UINT32 Address, IN UINT8 OpFlag, CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
 VOID          RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32  Data, IN AMD_CONFIG_PARAMS *StdHeader);
 VOID          ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
 VOID          ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE  *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
 VOID          ProgramFchSciMapTbl (IN SCI_MAP_CONTROL  *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
-VOID          ProgramFchGpioTbl (IN GPIO_CONTROL  *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID          ProgramFchGpioTbl (CONST IN GPIO_CONTROL  *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
 VOID          ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL  *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
 VOID          GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
 BOOLEAN       IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
@@ -436,4 +436,3 @@ FchPlatformSpiQe (
   );
 
 #endif
-

src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchPeLib.c

@@ -137,7 +137,7 @@ ProgramFchAcpiMmioTbl (
  */
 VOID
 ProgramFchGpioTbl (
-  IN       GPIO_CONTROL  *pGpioTbl,
+  CONST IN       GPIO_CONTROL  *pGpioTbl,
   IN       FCH_RESET_DATA_BLOCK *FchResetDataBlock
   )
 {

src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/PciLib.c

@@ -63,7 +63,7 @@ VOID
 WritePci (
   IN       UINT32                  Address,
   IN       UINT8                   OpFlag,
-  IN       VOID                    *Value,
+  CONST IN       VOID                    *Value,
   IN       AMD_CONFIG_PARAMS       *StdHeader
   )
 {
@@ -90,5 +90,3 @@ RwPci (
   rMask = ~Mask;
   LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c

@@ -55,7 +55,7 @@
  *
  *
  */
-ACPI_REG_WRITE FchInitResetAcpiMmioTable[] =
+CONST ACPI_REG_WRITE FchInitResetAcpiMmioTable[] =
 {
   {00, 00, 0xB0, 0xAC},
   //
@@ -121,5 +121,3 @@ ProgramFchHwAcpiResetP (
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c

@@ -75,7 +75,7 @@ CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = {
  *  InitReset Phase Data Block Default (Failsafe)
  *----------------------------------------------------------------
  */
-FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
+CONST FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
   NULL,                  // StdHeader
   { TRUE,
     TRUE,
@@ -181,5 +181,3 @@ FCH_RESET_DATA_BLOCK   InitResetCfgDefault = {
   FALSE,                 // QeEnabled
   NULL                   // OemResetProgrammingTablePtr
 };
-
-

src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c

@@ -47,13 +47,13 @@
 #define FILECODE PROC_FCH_SPI_FAMILY_YANGTZE_YANGTZELPCRESETSERVICE_FILECODE
 #define SPI_BASE UserOptions.FchBldCfg->CfgSpiRomBaseAddress
 
-SPI_CONTROLLER_PROFILE SpiControllerProfile[4] = {
+CONST SPI_CONTROLLER_PROFILE SpiControllerProfile[4] = {
   {128, 100, 100, 100, 100},
   {128,  66,  66,  66,  66},
   {128,  33,  33,  33,  33},
   {128,  16,  16,  16,  16},
   };
-SPI_DEVICE_PROFILE DefaultSpiDeviceTable[] = {
+CONST SPI_DEVICE_PROFILE DefaultSpiDeviceTable[] = {
   //JEDEC_ID,RomSize,SecSize;MaxNormal;MaxFast;MaxDual;MaxQuad;QeReadReg;QeWriteReg;QeRegSize;QeLocation;
   {0x001524C2, 2 << 20, 4096,  33, 108, 150, 300, 0x05, 0x01, 0x1, 0x0040}, //Macronix_MX25L1635D
   {0x001525C2, 2 << 20, 4096,  33, 108, 160, 432, 0x05, 0x01, 0x1, 0x0040}, //Macronix_MX25L1635E
@@ -86,7 +86,7 @@ SPI_DEVICE_PROFILE DefaultSpiDeviceTable[] = {
  *
  *
  */
-REG8_MASK FchInitYangtzeResetLpcPciTable[] =
+CONST REG8_MASK FchInitYangtzeResetLpcPciTable[] =
 {
   //
   // LPC Device (Bus 0, Dev 20, Func 3)
@@ -814,4 +814,3 @@ FchPlatformSpiQe (
   }
   return FALSE;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/Gnb.h

@@ -145,8 +145,8 @@ typedef enum {
 typedef struct _GNB_SERVICE {
   GNB_SERVICE_ID        ServiceId;        ///< Service ID
   UINT64                Family;           ///< CPU family
-  VOID                  *ServiceProtocol; ///< Service protocol
+  CONST VOID                  *ServiceProtocol; ///< Service protocol
-  struct  _GNB_SERVICE  *NextService;     ///< Pointer to next service
+  CONST struct  _GNB_SERVICE  *NextService;     ///< Pointer to next service
 } GNB_SERVICE;
 
 /// GNB SMU Firmware Pointers

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbPcie.h

@@ -191,7 +191,7 @@ typedef struct {
 
 /// Table Register Entry
 typedef struct {
-  PCIE_PORT_REGISTER_ENTRY  *Table;                     ///< Table
+  CONST PCIE_PORT_REGISTER_ENTRY  *Table;                     ///< Table
   UINT32                    Length;                     ///< Length
 } PCIE_PORT_REGISTER_TABLE_HEADER;
 
@@ -204,7 +204,7 @@ typedef struct {
 
 /// Table Register Entry
 typedef struct {
-  PCIE_HOST_REGISTER_ENTRY  *Table;                     ///< Table
+  CONST PCIE_HOST_REGISTER_ENTRY  *Table;                     ///< Table
   UINT32                    Length;                     ///< Length
 } PCIE_HOST_REGISTER_TABLE_HEADER;
 
@@ -384,7 +384,7 @@ typedef struct {
   UINT8                   EngineType;                   ///< Engine Type
   UINT8                   NumberOfEngines;              ///< Number of engines to configure
   UINT8                   NumberOfConfigurations;       ///< Number of possible configurations
-  UINT8                   *ConfigTable;                 ///< Pointer to config table
+  CONST UINT8                   *ConfigTable;                 ///< Pointer to config table
 } PCIe_LANE_ALLOC_DESCRIPTOR;
 
 /// Lane Control

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c

@@ -510,11 +510,11 @@ AGESA_STATUS
 GnbLibLocateService (
   IN       GNB_SERVICE_ID       ServiceId,
   IN       UINT8                SocketId,
-  IN       VOID                 **ServiceProtocol,
+  CONST IN       VOID                 **ServiceProtocol,
   IN       AMD_CONFIG_PARAMS    *StdHeader
   )
 {
-  GNB_SERVICE     *SeviceEntry;
+  CONST GNB_SERVICE     *SeviceEntry;
   CPU_LOGICAL_ID  LogicalId;
   SeviceEntry = ServiceTable;
   GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader);
@@ -527,4 +527,3 @@ GnbLibLocateService (
   }
   return AGESA_UNSUPPORTED;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.h

@@ -149,7 +149,7 @@ AGESA_STATUS
 GnbLibLocateService (
   IN       GNB_SERVICE_ID       ServiceId,
   IN       UINT8                SocketId,
-  IN       VOID                 **ServiceProtocol,
+  CONST IN       VOID                 **ServiceProtocol,
   IN       AMD_CONFIG_PARAMS    *StdHeader
   );
 

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c

@@ -146,12 +146,10 @@ GnbFmTimeStamp (
 
   GnbHandle = GnbGetHandle (StdHeader);
 
-  Status = GnbLibLocateService (GnbFamTsService, GnbGetSocketId (GnbHandle), (VOID **)&GnbFamTsFunc, StdHeader);
+  Status = GnbLibLocateService (GnbFamTsService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbFamTsFunc, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GnbFamTsFunc->GnbFmTimeStamp (StdHeader);
   }
   return 0;
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c

@@ -99,7 +99,7 @@ PcieFmConfigureEnginesLaneAllocation (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
-  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId);
@@ -135,7 +135,7 @@ PcieFmGetCoreConfigurationValue (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
-  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature,  ConfigurationValue);
@@ -170,7 +170,7 @@ PcieFmCheckPortPciDeviceMapping (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
@@ -203,7 +203,7 @@ PcieFmDebugGetCoreConfigurationString (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue);
@@ -233,7 +233,7 @@ PcieFmDebugGetWrapperNameString (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper);
@@ -264,7 +264,7 @@ PcieFmDebugGetHostRegAddressSpaceString (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame);
@@ -299,7 +299,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine);
@@ -330,7 +330,7 @@ PcieFmMapPortPciAddress (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmMapPortPciAddress (Engine);
@@ -358,7 +358,7 @@ PcieFmGetComplexDataLength (
 {
   AGESA_STATUS              Status;
   PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
-  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader);
@@ -388,7 +388,7 @@ PcieFmBuildComplexConfiguration (
 {
   AGESA_STATUS              Status;
   PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
-  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
@@ -419,7 +419,7 @@ PcieFmGetLinkSpeedCap (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine);
@@ -449,7 +449,7 @@ PcieFmGetNativePhyLaneBitmap (
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
   Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
-  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine);
@@ -479,7 +479,7 @@ PcieFmSetLinkSpeedCap (
   PCIe_FAM_INIT_SERVICES  *PcieInitService;
 
   Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
-  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
@@ -505,11 +505,10 @@ PcieFmGetSbConfigInfo (
 {
   AGESA_STATUS              Status;
   PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
-  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader);
   }
   return Status;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c

@@ -94,7 +94,7 @@ GnbFmCheckIommuPresent (
 {
   AGESA_STATUS              Status;
   GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
-  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader);
@@ -124,7 +124,7 @@ GnbFmCreateIvrsEntry (
 {
   AGESA_STATUS              Status;
   GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
-  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader);
@@ -155,7 +155,7 @@ GfxFmMapEngineToDisplayPath (
   GFX_FAM_SERVICES          *GfxFamilyService;
   GNB_HANDLE                *GnbHandle;
   GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
-  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx));
+  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GfxFamilyService->GfxMapEngineToDisplayPath (Engine, DisplayPathList, Gfx);
@@ -184,7 +184,7 @@ GfxFmCalculateClock (
   GFX_FAM_SERVICES          *GfxFamilyService;
   GNB_HANDLE                *GnbHandle;
   GnbHandle = GnbGetHandle (StdHeader);
-  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, StdHeader);
+  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GfxFamilyService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GfxFamilyService->GfxCalculateClock (Did, StdHeader);
@@ -210,7 +210,7 @@ GfxFmDisableController (
   GFX_FAM_SERVICES          *GfxFamilyService;
   GNB_HANDLE                *GnbHandle;
   GnbHandle = GnbGetHandle (StdHeader);
-  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, StdHeader);
+  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GfxFamilyService, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     GfxFamilyService->GfxDisableController (StdHeader);
@@ -234,12 +234,10 @@ GfxFmIsVbiosPosted (
   GFX_FAM_SERVICES          *GfxFamilyService;
   GNB_HANDLE                *GnbHandle;
   GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
-  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx));
+  Status = GnbLibLocateService (GfxFamService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GfxFamilyService, GnbLibGetHeader (Gfx));
   ASSERT (Status == AGESA_SUCCESS);
   if (Status == AGESA_SUCCESS) {
     return GfxFamilyService->GfxIsVbiosPosted (Gfx);
   }
   return TRUE;
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c

@@ -132,7 +132,7 @@ GfxIntegratedCopyDisplayInfo (
   IN       GFX_PLATFORM_CONFIG         *Gfx
   );
 
-EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
+CONST EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
   {
     ConnectorTypeDP,
     DEVICE_DFP,
@@ -233,7 +233,7 @@ EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
   },
 };
 
-UINT8 ConnectorNumerArray[] = {
+CONST UINT8 ConnectorNumerArray[] = {
 //  DP    eDP   SDVI-D  DDVI-D  HDMI   VGA   LVDS   Auto (eDP, LVDS, DP-to-LVDS)
     6,    1,    6,      6,      6,     1,    1,     2
 };
@@ -247,7 +247,7 @@ UINT8 ConnectorNumerArray[] = {
  * @retval    Pointer to EXT_CONNECTOR_INFO
  * @retval    NULL if connector type unknown.
  */
-STATIC EXT_CONNECTOR_INFO*
+STATIC CONST EXT_CONNECTOR_INFO*
 GfxIntegratedExtConnectorInfo (
   IN       UINT8                         ConnectorType
   )
@@ -261,7 +261,7 @@ GfxIntegratedExtConnectorInfo (
   return NULL;
 }
 
-EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
+CONST EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
   {
     DEVICE_CRT,
     1,
@@ -322,7 +322,7 @@ EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
  * @retval    Pointer to EXT_DISPLAY_DEVICE_INFO
  * @retval    NULL if can not get display device info
  */
-STATIC EXT_DISPLAY_DEVICE_INFO*
+STATIC CONST EXT_DISPLAY_DEVICE_INFO*
 GfxIntegratedExtDisplayDeviceInfo (
   IN       UINT8                         DisplayDeviceEnum,
   IN       UINT8                         DisplayDeviceIndex
@@ -412,7 +412,7 @@ GfxIntegratedDdiInterfaceCallback (
   )
 {
   CONNECTOR_ENUM_INFO     *ConnectorEnumInfo;
-  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  CONST EXT_CONNECTOR_INFO      *ExtConnectorInfo;
   ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer;
   ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
   if (ExtConnectorInfo == NULL) {
@@ -452,8 +452,8 @@ GfxIntegratedEnumConnectorsForDevice (
 {
   UINT8                   DisplayDeviceIndex;
   CONNECTOR_ENUM_INFO     ConnectorEnumInfo;
-  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  CONST EXT_CONNECTOR_INFO      *ExtConnectorInfo;
-  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  CONST EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
   AGESA_STATUS            Status;
   UINT8                   ConnectorIdArray[sizeof (ConnectorNumerArray)];
   ConnectorEnumInfo.Status = AGESA_SUCCESS;
@@ -529,8 +529,8 @@ GfxIntegratedCopyDisplayInfo (
   IN       GFX_PLATFORM_CONFIG         *Gfx
   )
 {
-  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  CONST EXT_CONNECTOR_INFO      *ExtConnectorInfo;
-  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  CONST EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
   ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
   ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId);
   DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8);

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h

@@ -71,7 +71,7 @@
   extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED      PcieCheckPortPcieLaneCanBeMuxedKB;
 
 
-  PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolKB = {
+  CONST PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolKB = {
     PcieGetComplexDataLengthKB,
     PcieBuildComplexConfigurationKB,
     PcieConfigureEnginesLaneAllocationKB,
@@ -81,7 +81,7 @@
     PcieGetSbConfigInfoKB
   };
 
-  GNB_SERVICE GnbPcieCongigServicesKB = {
+  CONST GNB_SERVICE GnbPcieCongigServicesKB = {
     GnbPcieFamConfigService,
     AMD_FAMILY_KB,
     &GnbPcieConfigProtocolKB,
@@ -97,14 +97,14 @@
   extern F_PCIEFMGETNATIVEPHYLANEBITMAP           PcieGetNativePhyLaneBitmapKB;
   extern F_PCIEFMSETLINKSPEEDCAP                  PcieSetLinkSpeedCapV4;
 
-  PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolKB = {
+  CONST PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolKB = {
     PcieGetCoreConfigurationValueKB,
     PcieGetLinkSpeedCapKB,
     PcieGetNativePhyLaneBitmapKB,
     PcieSetLinkSpeedCapV4
   };
 
-  GNB_SERVICE GnbPcieInitServicesKB = {
+  CONST GNB_SERVICE GnbPcieInitServicesKB = {
     GnbPcieFamInitService,
     AMD_FAMILY_KB,
     &GnbPcieInitProtocolKB,
@@ -121,13 +121,13 @@
       extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING          PcieDebugGetWrapperNameStringKB;
       extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING    PcieDebugGetCoreConfigurationStringKB;
 
-      PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolKB = {
+      CONST PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolKB = {
         PcieDebugGetHostRegAddressSpaceStringKB,
         PcieDebugGetWrapperNameStringKB,
         PcieDebugGetCoreConfigurationStringKB
       };
 
-      GNB_SERVICE GnbPcieDebugServicesKB = {
+      CONST GNB_SERVICE GnbPcieDebugServicesKB = {
         GnbPcieFamDebugService,
         AMD_FAMILY_KB,
         &GnbPcieDebugProtocolKB,
@@ -143,12 +143,12 @@
   extern F_GNB_REGISTER_ACCESS  GnbRegisterReadKB;
   extern F_GNB_REGISTER_ACCESS  GnbRegisterWriteKB;
 
-  GNB_REGISTER_SERVICE GnbRegisterAccessProtocolKB = {
+  CONST GNB_REGISTER_SERVICE GnbRegisterAccessProtocolKB = {
     GnbRegisterReadKB,
     GnbRegisterWriteKB
   };
 
-  GNB_SERVICE GnbRegisterAccessServicesKB = {
+  CONST GNB_SERVICE GnbRegisterAccessServicesKB = {
     GnbRegisterAccessService,
     AMD_FAMILY_KB,
     &GnbRegisterAccessProtocolKB,
@@ -162,14 +162,14 @@
   extern F_GNBURASERVICESET GnbUraSetKB;
   extern F_GNBURASERVICESTREAMSET GnbUraStreamSetKB;
 
-  GNB_URA_SERVICE GnbUraProtocolKB = {
+  CONST GNB_URA_SERVICE GnbUraProtocolKB = {
     GnbUraLocateRegTblKB,
     GnbUraGetKB,
     GnbUraSetKB,
     GnbUraStreamSetKB
   };
 
-  GNB_SERVICE GnbUraServicesKB = {
+  CONST GNB_SERVICE GnbUraServicesKB = {
     GnbUraService,
     AMD_FAMILY_KB,
     &GnbUraProtocolKB,
@@ -183,14 +183,14 @@
   extern F_GFXCALCULATECLOCK         GfxCalculateClockKB;
   extern F_GFXISVBIOSPOSTED          GfxIsVbiosPostedKB;
 
-  GFX_FAM_SERVICES GfxFamilyServiceProtocolKB = {
+  CONST GFX_FAM_SERVICES GfxFamilyServiceProtocolKB = {
     GfxMapEngineToDisplayPathKB,
     GfxDisableControllerKB,
     GfxCalculateClockKB,
     GfxIsVbiosPostedKB
   };
 
-  GNB_SERVICE GfxFamilyServicesKB = {
+  CONST GNB_SERVICE GfxFamilyServicesKB = {
     GfxFamService,
     AMD_FAMILY_KB,
     &GfxFamilyServiceProtocolKB,
@@ -201,11 +201,11 @@
 
   extern F_GNBTIMESTAMP GnbTimeStampKB;
 
-  GNB_FAM_TS_SERVICES GnbFamTsProtocolKB = {
+  CONST GNB_FAM_TS_SERVICES GnbFamTsProtocolKB = {
     GnbTimeStampKB,
   };
 
-  GNB_SERVICE GnbFamTsServicesKB = {
+  CONST GNB_SERVICE GnbFamTsServicesKB = {
     GnbFamTsService,
     AMD_FAMILY_KB,
     &GnbFamTsProtocolKB,
@@ -217,11 +217,11 @@
 
   extern F_PCIE_MAXPAYLOAD_SETTING  PcieMaxPayloadKB;
 
-  PCIE_MAXPAYLOAD_SERVICE PcieMaxPayloadProtocolKB = {
+  CONST PCIE_MAXPAYLOAD_SERVICE PcieMaxPayloadProtocolKB = {
     PcieMaxPayloadKB
   };
 
-  GNB_SERVICE PcieMaxPayloadServicesKB = {
+  CONST GNB_SERVICE PcieMaxPayloadServicesKB = {
     GnbPcieMaxPayloadService,
     AMD_FAMILY_KB,
     &PcieMaxPayloadProtocolKB,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h

@@ -45,7 +45,7 @@
 #ifndef _GNBSMUFIRMWAREKB_H_
 #define _GNBSMUFIRMWAREKB_H_
 
-UINT32  FirmwareKBHeader [] = {
+CONST UINT32  FirmwareKBHeader [] = {
   0x554D535F,
   0x554D535F,
   0x0001F984,
@@ -60,7 +60,7 @@ UINT32  FirmwareKBHeader [] = {
   0x00000000,
 };
 
-UINT32  FirmwareKB[] = {
+CONST UINT32  FirmwareKB[] = {
  0x74ca8b03,
  0x2636e501,
  0xc490b115,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c

@@ -80,7 +80,7 @@
  *----------------------------------------------------------------------------------------
  */
 
-GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB [] = {
+CONST GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB [] = {
   GNB_ENTRY_RMW (
     D0F0x98_x07_TYPE,
     D0F0x98_x07_ADDRESS,
@@ -96,7 +96,7 @@ GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB [] = {
   GNB_ENTRY_TERMINATE
 };
 
-GNB_TABLE ROMDATA GnbEarlyInitTableKB [] = {
+CONST GNB_TABLE ROMDATA GnbEarlyInitTableKB [] = {
   // Set SVI2
   GNB_ENTRY_PROPERTY_RMW (
     TABLE_PROPERTY_SVI2,
@@ -196,7 +196,7 @@ GNB_TABLE ROMDATA GnbEarlyInitTableKB [] = {
   GNB_ENTRY_TERMINATE
 };
 
-GNB_TABLE ROMDATA GnbEnvInitTableKB [] = {
+CONST GNB_TABLE ROMDATA GnbEnvInitTableKB [] = {
   //---------------------------------------------------------------------------
 
   // SMU Enable Thermal Controller
@@ -364,7 +364,7 @@ GNB_TABLE ROMDATA GnbEnvInitTableKB [] = {
   GNB_ENTRY_TERMINATE
 };
 
-GNB_TABLE ROMDATA GnbMidInitTableKB [] = {
+CONST GNB_TABLE ROMDATA GnbMidInitTableKB [] = {
 //---------------------------------------------------------------------------
 // ORB clock gating
   GNB_ENTRY_PROPERTY_RMW (

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c

@@ -74,7 +74,7 @@ GnbUraLocateRegTblKB (
  *----------------------------------------------------------------------------------------
  */
 
-REG_FIELD_TABLE_STRUCT  UraTableKB = {
+CONST REG_FIELD_TABLE_STRUCT  UraTableKB = {
   {0xC2100000, 0x4, 0},
   {0, 1, FIELD_OFFSET(RxSmuIntReq ,BfxSmuIntToggle)},
   {1, 16, FIELD_OFFSET(RxSmuIntReq ,BfxSmuServiceIndex)},
@@ -118,5 +118,3 @@ GnbUraLocateRegTblKB (
   *UraTableAddress = (UINT32)((UINTN)(&UraTableKB));
   return;
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c

@@ -95,7 +95,7 @@ PcieGetNativePhyLaneBitmapKB (
 // Complex configuration
 //
 
-KB_COMPLEX_CONFIG ComplexDataKB = {
+CONST KB_COMPLEX_CONFIG ComplexDataKB = {
   //Silicon
   {
     {
@@ -345,7 +345,7 @@ KB_COMPLEX_CONFIG ComplexDataKB = {
 //
 // PCIe lane allocation  GPP
 //
-UINT8 ROMDATA GppPortLaneConfigurationTableKB [] = {
+CONST UINT8 ROMDATA GppPortLaneConfigurationTableKB [] = {
   UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 4,              7,              0,            3,
   UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 6,              7,              4,              5,              0,            3,
   UNUSED_LANE_ID, UNUSED_LANE_ID, 7,              7,              6,              6,              4,              5,              0,            3,
@@ -355,14 +355,14 @@ UINT8 ROMDATA GppPortLaneConfigurationTableKB [] = {
 //
 // DDI lane allocation  DDI
 //
-UINT8 ROMDATA DdiLaneConfigurationTableKB [] = {
+CONST UINT8 ROMDATA DdiLaneConfigurationTableKB [] = {
    0,            3,             4,             7,             8,             11
 };
 
 //
 // PCIe lane allocation  desfriptors
 //
-PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[] = {
+CONST PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[] = {
   {
     0,
     GPP_WRAP_ID,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c

@@ -136,7 +136,7 @@ PcieGetSbConfigInfoKB (
 //
 // Default port dev map
 //
-UINT8 ROMDATA DefaultPortDevMap [] = {
+CONST UINT8 ROMDATA DefaultPortDevMap [] = {
   DEVFUNC (2, 1),
   DEVFUNC (2, 2),
   DEVFUNC (2, 3),
@@ -147,7 +147,7 @@ UINT8 ROMDATA DefaultPortDevMap [] = {
 //
 // Default apic config
 //
-APIC_DEVICE_INFO ROMDATA DefaultIoapicConfig [] = {
+CONST APIC_DEVICE_INFO ROMDATA DefaultIoapicConfig [] = {
   {0, 0, 0x18},
   {1, 0, 0x19},
   {2, 0, 0x1A},
@@ -622,5 +622,3 @@ PcieGetSbConfigInfoKB (
 {
   return AGESA_UNSUPPORTED;
 }
-
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c

@@ -268,7 +268,7 @@ PciePhyIsolationKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Exit\n");
 }
 
-UINT8 LaneMuxSelectorArrayKB[] = { 7, 6, 5, 4, 3, 2, 1, 0 };
+CONST UINT8 LaneMuxSelectorArrayKB[] = { 7, 6, 5, 4, 3, 2, 1, 0 };
 
 /*----------------------------------------------------------------------------------------*/
 /**
@@ -935,4 +935,3 @@ PcieEarlyInterfaceKB (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c

@@ -74,7 +74,7 @@
  *----------------------------------------------------------------------------------------
  */
 
-STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
+STATIC CONST PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
   {
     PHY_SPACE (0, 0, D0F0xE4_PHY_4440_ADDRESS),
     D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK,
@@ -98,7 +98,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB  = {
   ARRAY_SIZE(PcieInitEarlyTable)
   };
 
-STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
+STATIC CONST PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
   {
     D0F0xE4_CORE_0020_ADDRESS,
     D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
@@ -150,7 +150,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB  = {
   };
 
 
-STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
+STATIC CONST PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
   {
     DxFxxE4_x70_ADDRESS,
     DxFxxE4_x70_RxRcbCplTimeoutMode_MASK,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h

@@ -43,7 +43,7 @@
 #ifndef _EXCEL925_H_
 #define _EXCEL925_H_
 
-UINT8 excel925[] = {
+CONST UINT8 excel925[] = {
   0x21, 0x53, 0x43, 0x53, 0x4B, 0x41, 0x42, 0x49, 0x4E, 0x49, 0x20, 0x20, 0x56, 0x30, 0x2E, 0x30,
   0x2E, 0x30, 0x2E, 0x31, 0x1 , 0x00, 0x00, 0x4 , 0x00, 0x3 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x16, 0x2 , 0x1 , 0xA5, 0xF7, 0x2D, 0x83, 0x4E, 0xC3, 0xC3, 0x40, 0x00, 0x00, 0x00, 0x00,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c

@@ -148,7 +148,7 @@ BOOLEAN
 PcieUtilSearchArray (
   IN      UINT8                         *Buf1,
   IN      UINTN                         Buf1Length,
-  IN      UINT8                         *Buf2,
+  CONST IN      UINT8                         *Buf2,
   IN      UINTN                         Buf2Length
   )
 {
@@ -156,7 +156,7 @@ PcieUtilSearchArray (
   CurrentBuf1Ptr = Buf1;
   while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
     UINT8 *SourceBufPtr;
-    UINT8 *PatternBufPtr;
+    CONST UINT8 *PatternBufPtr;
     UINTN PatternBufLength;
     SourceBufPtr = CurrentBuf1Ptr;
     PatternBufPtr = Buf2;
@@ -522,7 +522,7 @@ PcieUtilGetWrapperLaneBitMap (
 
 VOID
 PciePortProgramRegisterTable (
-  IN      PCIE_PORT_REGISTER_ENTRY    *Table,
+  CONST IN      PCIE_PORT_REGISTER_ENTRY    *Table,
   IN      UINTN                       Length,
   IN      PCIe_ENGINE_CONFIG          *Engine,
   IN      BOOLEAN                     S3Save,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h

@@ -65,7 +65,7 @@ BOOLEAN
 PcieUtilSearchArray (
   IN      UINT8                         *Buf1,
   IN      UINTN                         Buf1Length,
-  IN      UINT8                         *Buf2,
+  CONST IN      UINT8                         *Buf2,
   IN      UINTN                         Buf2Length
   );
 
@@ -109,7 +109,7 @@ PcieUtilGetWrapperLaneBitMap (
 
 VOID
 PciePortProgramRegisterTable (
-  IN      PCIE_PORT_REGISTER_ENTRY       *Table,
+  CONST IN      PCIE_PORT_REGISTER_ENTRY       *Table,
   IN      UINTN                          Length,
   IN      PCIe_ENGINE_CONFIG             *Engine,
   IN      BOOLEAN                        S3Save,

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c

@@ -334,7 +334,7 @@ PcieMaxPayloadInitCallback (
       (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) {
     EngineMaxPayload =  MAX_PAYLOAD;
     Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
-    Status = GnbLibLocateService (GnbPcieMaxPayloadService, Complex->SocketId, (VOID **)&PcieMaxPayloadProtocol, GnbLibGetHeader (Pcie));
+    Status = GnbLibLocateService (GnbPcieMaxPayloadService, Complex->SocketId, (CONST VOID **)&PcieMaxPayloadProtocol, GnbLibGetHeader (Pcie));
     if (Status ==  AGESA_SUCCESS) {
       EngineMaxPayload = PcieMaxPayloadProtocol->SetMaxPayload (Engine);
     }
@@ -373,4 +373,3 @@ PcieMaxPayloadInterface (
   IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Exit [0x%x]\n", AgesaStatus);
   return  AgesaStatus;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c

@@ -312,9 +312,9 @@ PcieTrainingDetectPresence (
   }
 }
 
-UINT8 FailPattern1 [] = {0x2a, 0x6};
+CONST UINT8 FailPattern1 [] = {0x2a, 0x6};
-UINT8 FailPattern2 [] = {0x2a, 0x9};
+CONST UINT8 FailPattern2 [] = {0x2a, 0x9};
-UINT8 FailPattern3 [] = {0x2a, 0xb};
+CONST UINT8 FailPattern3 [] = {0x2a, 0xb};
 
 /*----------------------------------------------------------------------------------------*/
 /**
@@ -798,4 +798,3 @@ PcieTraining (
   IDS_PERF_TIMESTAMP (TP_ENDGNBPCIETRAINING, GnbLibGetHeader (Pcie));
   return Status;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c

@@ -83,7 +83,7 @@ extern GNB_BUILD_OPTIONS GnbBuildOptions;
 AGESA_STATUS
 GnbSmuInitLibV7139_fun0 (
   IN       GNB_HANDLE           *GnbHandle,
-  IN       UINT8                *ScsDataPtr,
+  CONST IN       UINT8                *ScsDataPtr,
   IN       AMD_CONFIG_PARAMS    *StdHeader
   )
 {
@@ -146,7 +146,7 @@ GnbSmuInitLibV7139_fun1 (
   DevObject.StdHeader = StdHeader;
   DevObject.DevPciAddress = GnbGetHostPciAddress (GnbHandle);
 
-  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader);
+  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
   if (Status != AGESA_SUCCESS) {
     return Status;

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c

@@ -221,7 +221,7 @@ GnbSmuFirmwareLoadV7 (
   IDS_OPTION_HOOK (IDS_REPORT_SMU_FW_VERSION, &(Firmware->Version), StdHeader);
 
   GnbPciAddress = GnbGetHostPciAddress (GnbHandle);
-  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader);
+  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   DevObject.GnbHandle = GnbHandle;
@@ -327,4 +327,3 @@ GnbSmuFirmwareLoadV7 (
   IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV7 Exit\n");
   return AGESA_SUCCESS;
 }
-

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.h

@@ -109,7 +109,7 @@ GnbSmuFirmwareLoadV7 (
 AGESA_STATUS
 GnbSmuInitLibV7139_fun0(
   IN       GNB_HANDLE           *GnbHandle,
-  IN       UINT8                *ScsDataPtr,
+  CONST IN       UINT8                *ScsDataPtr,
   IN       AMD_CONFIG_PARAMS    *StdHeader
   );
 

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbTable/GnbTable.c

@@ -125,7 +125,7 @@ GnbProcessTable (
     WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE;
   }
 
-  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader);
+  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   while (*EntryPointer != GnbEntryTerminate) {

src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c

@@ -76,7 +76,7 @@
  *----------------------------------------------------------------------------------------
  */
 
-UINT8 RegisterDomainMap[] = {
+CONST UINT8 RegisterDomainMap[] = {
   0x0,          ///< Stub
   0x0,          ///< Stub
   0x64,         ///< 0x2
@@ -218,7 +218,7 @@ GnbUraGet (
   UINT32                    UraTableAddress;
 
   UraTable = NULL;
-  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader);
+  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (CONST VOID **)&GnbUraProtocol, Device->StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress);
@@ -253,7 +253,7 @@ GnbUraSet (
   URA_ENTRY                 *UraTable;
   UINT32                    UraTableAddress;
 
-  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader);
+  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (CONST VOID **)&GnbUraProtocol, Device->StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress);
@@ -295,7 +295,7 @@ GnbUraCombinedGet (
   URA_TOKEN               UraToken;
   UINT32                  Index;
 
-  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader);
+  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (CONST VOID **)&GnbUraProtocol, Device->StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress);
@@ -353,7 +353,7 @@ GnbUraCombinedSet (
   URA_TOKEN               UraToken;
   UINT32                  Index;
 
-  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (VOID **)&GnbUraProtocol, Device->StdHeader);
+  Status = GnbLibLocateService (GnbUraService, GnbGetSocketId (Device->GnbHandle), (CONST VOID **)&GnbUraProtocol, Device->StdHeader);
   ASSERT (Status == AGESA_SUCCESS);
 
   GnbUraProtocol->GnbUraLocateRegTbl (Device, &UraTableAddress);

src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c

@@ -198,7 +198,7 @@ MemNS3SetMemClkFreqValKB (
  *
  *----------------------------------------------------------------------------
  */
-PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
+CONST PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
   {MemNS3GetCSRKB, MemNS3SetCSRKB},
   {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb},
   {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb},
@@ -217,10 +217,10 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
   {MemNSaveHobDataUnb, MemNRestoreHobDataUnb}
 };
 
-MSR_SPECIAL_CASE MsrSpecialCaseFuncKB[] = {
+CONST MSR_SPECIAL_CASE MsrSpecialCaseFuncKB[] = {
   { MemNModdifyMtrrFixDramModEn, MemNModdifyMtrrFixDramModEn}
 };
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
+CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
   {{14,3, 1}, DO_NOT_CARE, 0, 0},
   {{0, 0, 0}, FUNC_2, 0x110, 0x00000020},
   {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF0703},
@@ -247,7 +247,7 @@ CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = {
   PciSpecialCaseFuncKB
 };
 
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = {
+CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = {
    // DCT 0
   {{7, 0, 1}, DCT0,   0x40,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
   {{7, 0, 1}, DCT0,   0x44,  0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK},
@@ -419,7 +419,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefKB = {
   PciSpecialCaseFuncKB
 };
 
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
+CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   // DCT0
   {{12, 2, 1}, DCT0,  BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
   {{1, 2, 1}, DCT0,   BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK},
@@ -613,7 +613,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefKB = {
   PciSpecialCaseFuncKB
 };
 
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = {
+CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = {
   {{0, 0, 0}, 0xC0010010, 0x00000000007F0000},
   {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
   {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
@@ -643,7 +643,7 @@ CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefKB = {
   MsrSpecialCaseFuncKB
 };
 
-VOID *MemS3RegListKB[] = {
+VOID * CONST MemS3RegListKB[] = {
   (VOID *)&S3PciPreSelfRefKB,
   NULL,
   (VOID *)&S3CPciPreSelfRefKB,

src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c

@@ -93,7 +93,7 @@ BOOLEAN
 STATIC
 MemPPSCGen (
   IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  CONST IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
   );
 
 BOOLEAN
@@ -557,7 +557,7 @@ BOOLEAN
 STATIC
 MemPPSCGen (
   IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  CONST IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
   )
 {
   UINT8 i;

src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttEdgeDetect.c

@@ -101,7 +101,7 @@ RDATA_GROUP (G1_PEICC)
  * Sweep Table For Byte Training without insertion delay
  *
 */
-DQS_POS_SWEEP_TABLE SweepTableByte[] =
+CONST DQS_POS_SWEEP_TABLE SweepTableByte[] =
 {
   //     Begin  End   Inc/Dec  Step  EndResult Edge
   {      0x00,  0x1F, INC_DELAY,  4, 0xFFFF,   LEFT_EDGE},  /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS
@@ -113,7 +113,7 @@ DQS_POS_SWEEP_TABLE SweepTableByte[] =
  * Sweep Table For Byte Training with insertion delay
  *
 */
-DQS_POS_SWEEP_TABLE InsSweepTableByte[] =
+CONST DQS_POS_SWEEP_TABLE InsSweepTableByte[] =
 {
   //     Begin  End   Inc/Dec  Step  EndResult Edge
   {      0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE},  /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL
@@ -400,7 +400,7 @@ MemTTrainDQSEdgeDetect (
 {
   MEM_NB_BLOCK         *NBPtr;
   DIE_STRUCT           *MCTPtr;
-  DQS_POS_SWEEP_TABLE  *SweepTablePtr;
+  CONST DQS_POS_SWEEP_TABLE  *SweepTablePtr;
   UINT8                SweepTableSize;
   SWEEP_INFO           SweepData;
   BOOLEAN              Status;
@@ -903,4 +903,3 @@ MemTDataEyeSave (
 
   return TRUE;
 }
-