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soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock

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Base code is based of Intel Alder Lake SOC code.

List of changes:

1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
	vol1 #621483, vol2 #640858

TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Ravi Sarawadi
2022-04-10 23:31:24 -07:00
committed by Subrata Banik
parent 3d79f7f13e
commit b8224f48fe
14 changed files with 1028 additions and 0 deletions
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22
src/soc/intel/meteorlake/bootblock/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/bootblock.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
void bootblock_soc_early_init(void)
{
bootblock_ioe_die_early_init();
bootblock_soc_die_early_init();
}
void bootblock_soc_init(void)
{
report_platform_info();
bootblock_soc_die_init();
}

9
src/soc/intel/meteorlake/bootblock/ioe_die.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/p2sb.h>
#include <soc/bootblock.h>
void bootblock_ioe_die_early_init(void)
{
ioe_p2sb_enable_bar();
}

155
src/soc/intel/meteorlake/bootblock/report_platform.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/cpu_ids.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/name.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
static struct {
u32 cpuid;
const char *name;
} cpu_table[] = {
{ CPUID_METEORLAKE_A0_1, "MeteorLake A0" },
{ CPUID_METEORLAKE_A0_2, "MeteorLake A0" },
};
static struct {
u16 mchid;
const char *name;
} mch_table[] = {
{ PCI_DID_INTEL_MTL_M_ID, "MeteorLake M" },
{ PCI_DID_INTEL_MTL_P_ID_1, "MeteorLake P" },
{ PCI_DID_INTEL_MTL_P_ID_2, "MeteorLake P" },
};
static struct {
u16 espiid;
const char *name;
} pch_table[] = {
{ PCI_DID_INTEL_MTL_ESPI_0, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_1, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_2, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_3, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_4, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_5, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_6, "MeteorLake SOC" },
{ PCI_DID_INTEL_MTL_ESPI_7, "MeteorLake SOC" },
};
static struct {
u16 igdid;
const char *name;
} igd_table[] = {
{ PCI_DID_INTEL_MTL_M_GT2, "MeteorLake-M GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_1, "MeteorLake-P GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" },
};
static inline uint8_t get_dev_revision(pci_devfn_t dev)
{
return pci_read_config8(dev, PCI_REVISION_ID);
}
static inline uint16_t get_dev_id(pci_devfn_t dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
static void report_cpu_info(void)
{
u32 i, cpu_id, cpu_feature_flag;
char cpu_name[49];
int vt, txt, aes;
static const char *const mode[] = {"NOT ", ""};
const char *cpu_type = "Unknown";
fill_processor_name(cpu_name);
cpu_id = cpu_get_cpuid();
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
}
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
cpu_id, cpu_type, get_current_microcode_rev());
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = !!(cpu_feature_flag & CPUID_AES);
txt = !!(cpu_feature_flag & CPUID_SMX);
vt = !!(cpu_feature_flag & CPUID_VMX);
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
}
static void report_mch_info(void)
{
int i;
pci_devfn_t dev = PCI_DEV_ROOT;
uint16_t mchid = get_dev_id(dev);
const char *mch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
if (mch_table[i].mchid == mchid) {
mch_type = mch_table[i].name;
break;
}
}
printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
mchid, get_dev_revision(dev), mch_type);
}
static void report_pch_info(void)
{
int i;
pci_devfn_t dev = PCI_DEV_ESPI;
uint16_t espiid = get_dev_id(dev);
const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].espiid == espiid) {
pch_type = pch_table[i].name;
break;
}
}
printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
espiid, get_dev_revision(dev), pch_type);
}
static void report_igd_info(void)
{
int i;
pci_devfn_t dev = PCI_DEV_IGD;
uint16_t igdid = get_dev_id(dev);
const char *igd_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
if (igd_table[i].igdid == igdid) {
igd_type = igd_table[i].name;
break;
}
}
printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
igdid, get_dev_revision(dev), igd_type);
}
void report_platform_info(void)
{
report_cpu_info();
report_mch_info();
report_pch_info();
report_igd_info();
}

140
src/soc/intel/meteorlake/bootblock/soc_die.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>
#define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xA00
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
#define PCR_PSFX_TO_SHDW_BAR3 0xC
#define PCR_PSFX_TO_SHDW_BAR4 0x10
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
static void soc_die_config_pwrmbase(void)
{
/*
* Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register
*/
pci_and_config16(PCI_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */
pci_write_config32(PCI_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */
pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
static void soc_die_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
/* IO Decode Range */
if (CONFIG(DRIVERS_UART_8250IO))
lpc_io_setup_comm_a_b();
/* IO Decode Enable */
lpc_enable_fixed_io_ranges(io_enables);
/* Program generic IO Decode Range */
pch_enable_lpc();
}
void bootblock_soc_die_early_init(void)
{
const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
};
bootblock_systemagent_early_init();
/* Enable MCHBAR early, needed by IOC driver */
sa_set_pci_bar(soc_fixed_pci_resources, ARRAY_SIZE(soc_fixed_pci_resources));
fast_spi_cache_bios_region();
soc_die_early_iorange_init();
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
/*
* Perform P2SB configuration before any another controller initialization as the
* controller might want to perform PCR settings.
*/
p2sb_enable_bar();
p2sb_configure_hpet();
fast_spi_early_init(SPI_BASE_ADDRESS);
gspi_early_bar_init();
/*
* Enabling SoC PMC PWRM Base for accessing
* Global Reset Cause Register.
*/
soc_die_config_pwrmbase();
}
static void soc_die_config_acpibase(void)
{
uint32_t pmc_reg_value;
uint32_t pmc_base_reg = PCR_PSF8_TO_SHDW_PMC_REG_BASE;
pmc_reg_value = pcr_read32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
if (pmc_reg_value != 0xffffffff) {
/* Disable Io Space before changing the address */
pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
/* Program ABASE in PSF3 PMC space BAR4 */
pcr_write32(PID_PSF8, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
ACPI_BASE_ADDRESS);
/* Enable IO Space */
pcr_rmw32(PID_PSF8, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
}
}
void bootblock_soc_die_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
* GPE0_STS, GPE0_EN registers.
*/
soc_die_config_acpibase();
/* Set up GPE configuration */
pmc_gpe_init();
enable_rtc_upper_bank();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure();
}