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intel SMI handlers: Refactor GPI SMI/SCI routing

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Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.

Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This commit is contained in:
Kyösti Mälkki
2014-12-29 11:32:27 +02:00
parent 189f3ba974
commit b85a87b7d6
23 changed files with 167 additions and 317 deletions
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2
src/southbridge/intel/ibexpeak/lpc.c
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@ -166,7 +166,7 @@ static void pch_gpi_routing(device_t dev)
reg32 |= (config->gpi14_routing & 0x03) << 28;
reg32 |= (config->gpi15_routing & 0x03) << 30;
pci_write_config32(dev, 0xb8, reg32);
pci_write_config32(dev, GPIO_ROUT, reg32);
}
static void pch_power_options(device_t dev)