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intel SMI handlers: Refactor GPI SMI/SCI routing

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Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.

Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This commit is contained in:
Kyösti Mälkki
2014-12-29 11:32:27 +02:00
parent 189f3ba974
commit b85a87b7d6
23 changed files with 167 additions and 317 deletions
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6
src/southbridge/intel/ibexpeak/pch.h
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@@ -71,6 +71,7 @@ int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if CONFIG_ELOG
void pch_log_state(void);
#endif
@@ -133,7 +134,12 @@ void southbridge_configure_default_intmap(void);
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT 0xb8
#define GPI_DISABLE 0x00
#define GPI_IS_SMI 0x01
#define GPI_IS_SCI 0x02
#define GPI_IS_NMI 0x03
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61