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intel SMI handlers: Refactor GPI SMI/SCI routing

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Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.

Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This commit is contained in:
Kyösti Mälkki
2014-12-29 11:32:27 +02:00
parent 189f3ba974
commit b85a87b7d6
23 changed files with 167 additions and 317 deletions
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36
src/southbridge/intel/ibexpeak/smihandler.c
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@@ -75,6 +75,42 @@ void tseg_relocate(void **ptr)
}
#endif
static void alt_gpi_mask(u16 clr, u16 set)
{
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
alt_gp &= ~clr;
alt_gp |= set;
outw(alt_gp, pmbase + ALT_GP_SMI_EN);
}
static void gpe0_mask(u32 clr, u32 set)
{
u32 gpe0 = inl(pmbase + GPE0_EN);
gpe0 &= ~clr;
gpe0 |= set;
outl(gpe0, pmbase + GPE0_EN);
}
void gpi_route_interrupt(u8 gpi, u8 mode)
{
u32 gpi_rout;
if (gpi >= 16)
return;
alt_gpi_mask(1 << gpi, 0);
gpe0_mask(1 << (gpi+16), 0);
gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
gpi_rout &= ~(3 << (2 * gpi));
gpi_rout |= ((mode & 3) << (2 * gpi));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
if (mode == GPI_IS_SCI)
gpe0_mask(0, 1 << (gpi+16));
else if (mode == GPI_IS_SMI)
alt_gpi_mask(0, 1 << gpi);
}
/**
* @brief read and clear PM1_STS
* @return PM1_STS register