Change references to qemu in Coreboot-v2 calls to qemu-x86.
The patch was followed by these svn commands: svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force src/mainboard/emulation/qemu-i386/ src/mainboard/emulation/qemu-x86 svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86 Signed-off-by: Myles Watson <myles@pel.cs.byu.edu> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
committed by
Myles Watson
Myles Watson
parent
f2b380ad85
commit
b8c2aa2ce8
153
src/cpu/emulation/qemu-x86/northbridge.c
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153
src/cpu/emulation/qemu-x86/northbridge.c
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#include "northbridge.h"
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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best = new;
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}
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*best_p = best;
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}
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static uint32_t find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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uint32_t tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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return tolm;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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static const uint8_t ramregs[] = {
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0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
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};
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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unsigned long tomk, tolmk;
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unsigned char rambits;
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int i, idx;
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for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
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unsigned char reg;
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reg = pci_read_config8(mc_dev, ramregs[i]);
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/* these are ENDING addresses, not sizes.
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* if there is memory in this slot, then reg will be > rambits.
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* So we just take the max, that gives us total.
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* We take the highest one to cover for once and future coreboot
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* bugs. We warn about bugs.
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*/
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if (reg > rambits)
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rambits = reg;
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if (reg < rambits)
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printk_err("ERROR! register 0x%x is not set!\n",
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ramregs[i]);
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}
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if (rambits == 0) {
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printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n");
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rambits = 8;
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}
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printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
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tomk = rambits*8*1024;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory.
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*/
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tolmk = tomk;
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}
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, tolmk);
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}
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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}
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struct chip_operations cpu_emulation_qemu_x86_ops = {
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CHIP_NAME("QEMU Northbridge")
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.enable_dev = enable_dev,
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};
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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