ic2/designware: Move Intel i2c logic to shared driver
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Chris Ching
728
src/drivers/i2c/designware/dw_i2c.c
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728
src/drivers/i2c/designware/dw_i2c.c
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@ -0,0 +1,728 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2009 Vipin Kumar, ST Microelectronics
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* Copyright 2017 Google Inc.
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* Copyright 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpigen.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c_simple.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <string.h>
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#include <timer.h>
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#include "dw_i2c.h"
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/* Use a ~10ms timeout for various operations */
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#define DW_I2C_TIMEOUT_US 10000
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/* High and low times in different speed modes (in ns) */
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enum {
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/* SDA Hold Time */
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DEFAULT_SDA_HOLD_TIME = 300,
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/* Standard Speed */
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MIN_SS_SCL_HIGHTIME = 4000,
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MIN_SS_SCL_LOWTIME = 4700,
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/* Fast Speed */
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MIN_FS_SCL_HIGHTIME = 600,
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MIN_FS_SCL_LOWTIME = 1300,
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/* Fast Plus Speed */
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MIN_FP_SCL_HIGHTIME = 260,
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MIN_FP_SCL_LOWTIME = 500,
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/* High Speed */
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MIN_HS_SCL_HIGHTIME = 60,
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MIN_HS_SCL_LOWTIME = 160,
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};
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/* Frequency represented as ticks per ns. Can also be used to calculate
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* the number of ticks to meet a time target or the period. */
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struct freq {
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uint32_t ticks;
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uint32_t ns;
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};
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/* Control register definitions */
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enum {
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CONTROL_MASTER_MODE = (1 << 0),
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CONTROL_SPEED_SS = (1 << 1),
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CONTROL_SPEED_FS = (1 << 2),
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CONTROL_SPEED_HS = (3 << 1),
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CONTROL_SPEED_MASK = (3 << 1),
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CONTROL_10BIT_SLAVE = (1 << 3),
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CONTROL_10BIT_MASTER = (1 << 4),
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CONTROL_RESTART_ENABLE = (1 << 5),
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CONTROL_SLAVE_DISABLE = (1 << 6),
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};
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/* Command/Data register definitions */
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enum {
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CMD_DATA_CMD = (1 << 8),
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CMD_DATA_STOP = (1 << 9),
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};
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/* Status register definitions */
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enum {
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STATUS_ACTIVITY = (1 << 0),
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STATUS_TX_FIFO_NOT_FULL = (1 << 1),
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STATUS_TX_FIFO_EMPTY = (1 << 2),
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STATUS_RX_FIFO_NOT_EMPTY = (1 << 3),
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STATUS_RX_FIFO_FULL = (1 << 4),
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STATUS_MASTER_ACTIVITY = (1 << 5),
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STATUS_SLAVE_ACTIVITY = (1 << 6),
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};
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/* Enable register definitions */
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enum {
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ENABLE_CONTROLLER = (1 << 0),
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};
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/* Interrupt status register definitions */
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enum {
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INTR_STAT_RX_UNDER = (1 << 0),
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INTR_STAT_RX_OVER = (1 << 1),
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INTR_STAT_RX_FULL = (1 << 2),
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INTR_STAT_TX_OVER = (1 << 3),
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INTR_STAT_TX_EMPTY = (1 << 4),
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INTR_STAT_RD_REQ = (1 << 5),
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INTR_STAT_TX_ABORT = (1 << 6),
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INTR_STAT_RX_DONE = (1 << 7),
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INTR_STAT_ACTIVITY = (1 << 8),
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INTR_STAT_STOP_DET = (1 << 9),
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INTR_STAT_START_DET = (1 << 10),
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INTR_STAT_GEN_CALL = (1 << 11),
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};
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/* I2C Controller MMIO register space */
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struct dw_i2c_regs {
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uint32_t control;
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uint32_t target_addr;
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uint32_t slave_addr;
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uint32_t master_addr;
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uint32_t cmd_data;
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uint32_t ss_scl_hcnt;
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uint32_t ss_scl_lcnt;
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uint32_t fs_scl_hcnt;
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uint32_t fs_scl_lcnt;
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uint32_t hs_scl_hcnt;
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uint32_t hs_scl_lcnt;
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uint32_t intr_stat;
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uint32_t intr_mask;
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uint32_t raw_intr_stat;
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uint32_t rx_thresh;
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uint32_t tx_thresh;
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uint32_t clear_intr;
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uint32_t clear_rx_under_intr;
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uint32_t clear_rx_over_intr;
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uint32_t clear_tx_over_intr;
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uint32_t clear_rd_req_intr;
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uint32_t clear_tx_abrt_intr;
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uint32_t clear_rx_done_intr;
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uint32_t clear_activity_intr;
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uint32_t clear_stop_det_intr;
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uint32_t clear_start_det_intr;
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uint32_t clear_gen_call_intr;
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uint32_t enable;
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uint32_t status;
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uint32_t tx_level;
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uint32_t rx_level;
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uint32_t sda_hold;
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uint32_t tx_abort_source;
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uint32_t slv_data_nak_only;
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uint32_t dma_cr;
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uint32_t dma_tdlr;
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uint32_t dma_rdlr;
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uint32_t sda_setup;
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uint32_t ack_general_call;
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uint32_t enable_status;
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uint32_t fs_spklen;
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uint32_t hs_spklen;
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uint32_t clr_restart_det;
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uint32_t comp_param1;
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uint32_t comp_version;
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uint32_t comp_type;
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} __packed;
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static const struct i2c_descriptor {
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enum i2c_speed speed;
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struct freq freq;
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int min_thigh_ns;
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int min_tlow_ns;
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} speed_descriptors[] = {
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{
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.speed = I2C_SPEED_STANDARD,
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.freq = {
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.ticks = 100,
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.ns = 1000*1000,
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},
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.min_thigh_ns = MIN_SS_SCL_HIGHTIME,
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.min_tlow_ns = MIN_SS_SCL_LOWTIME,
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},
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{
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.speed = I2C_SPEED_FAST,
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.freq = {
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.ticks = 400,
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.ns = 1000*1000,
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},
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.min_thigh_ns = MIN_FS_SCL_HIGHTIME,
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.min_tlow_ns = MIN_FS_SCL_LOWTIME,
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},
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{
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.speed = I2C_SPEED_FAST_PLUS,
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.freq = {
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.ticks = 1,
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.ns = 1000,
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},
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.min_thigh_ns = MIN_FP_SCL_HIGHTIME,
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.min_tlow_ns = MIN_FP_SCL_LOWTIME,
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},
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{
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/* 100pF max capacitance */
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.speed = I2C_SPEED_HIGH,
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.freq = {
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.ticks = 3400,
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.ns = 1000*1000,
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},
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.min_thigh_ns = MIN_HS_SCL_HIGHTIME,
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.min_tlow_ns = MIN_HS_SCL_LOWTIME,
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},
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};
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static const struct soc_clock {
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int clk_speed_mhz;
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struct freq freq;
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} soc_clocks[] = {
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{
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.clk_speed_mhz = 120,
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.freq = {
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.ticks = 120,
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.ns = 1000,
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},
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},
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{
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.clk_speed_mhz = 133,
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.freq = {
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.ticks = 400,
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.ns = 3000,
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},
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},
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};
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static const struct i2c_descriptor *get_bus_descriptor(enum i2c_speed speed)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(speed_descriptors); i++)
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if (speed == speed_descriptors[i].speed)
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return &speed_descriptors[i];
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return NULL;
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}
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static const struct soc_clock *get_soc_descriptor(int ic_clk)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(soc_clocks); i++)
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if (ic_clk == soc_clocks[i].clk_speed_mhz)
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return &soc_clocks[i];
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return NULL;
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}
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static int counts_from_time(const struct freq *f, int ns)
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{
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return DIV_ROUND_UP(f->ticks * ns, f->ns);
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}
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static int counts_from_freq(const struct freq *fast, const struct freq *slow)
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{
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return DIV_ROUND_UP(fast->ticks * slow->ns, fast->ns * slow->ticks);
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}
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/* Enable this I2C controller */
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static void dw_i2c_enable(struct dw_i2c_regs *regs)
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{
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uint32_t enable = read32(®s->enable);
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if (!(enable & ENABLE_CONTROLLER))
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write32(®s->enable, enable | ENABLE_CONTROLLER);
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}
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/* Disable this I2C controller */
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static int dw_i2c_disable(struct dw_i2c_regs *regs)
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{
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uint32_t enable = read32(®s->enable);
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if (enable & ENABLE_CONTROLLER) {
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struct stopwatch sw;
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write32(®s->enable, enable & ~ENABLE_CONTROLLER);
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/* Wait for enable bit to clear */
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stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US);
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while (read32(®s->enable_status) & ENABLE_CONTROLLER)
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if (stopwatch_expired(&sw))
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return -1;
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}
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return 0;
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}
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/* Wait for this I2C controller to go idle for transmit */
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static int dw_i2c_wait_for_bus_idle(struct dw_i2c_regs *regs)
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{
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struct stopwatch sw;
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/* Start timeout for up to 16 bytes in FIFO */
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stopwatch_init_usecs_expire(&sw, 16 * DW_I2C_TIMEOUT_US);
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while (!stopwatch_expired(&sw)) {
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uint32_t status = read32(®s->status);
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/* Check for master activity and keep waiting */
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if (status & STATUS_MASTER_ACTIVITY)
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continue;
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/* Check for TX FIFO empty to indicate TX idle */
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if (status & STATUS_TX_FIFO_EMPTY)
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return 0;
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}
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/* Timed out while waiting for bus to go idle */
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return -1;
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}
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/* Transfer one byte of one segment, sending stop bit if requested */
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static int dw_i2c_transfer_byte(struct dw_i2c_regs *regs,
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const struct i2c_msg *segment,
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size_t byte, int send_stop)
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{
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struct stopwatch sw;
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uint32_t cmd = CMD_DATA_CMD; /* Read op */
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stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US);
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if (!(segment->flags & I2C_M_RD)) {
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/* Write op only: Wait for FIFO not full */
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while (!(read32(®s->status) & STATUS_TX_FIFO_NOT_FULL)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "I2C transmit timeout\n");
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return -1;
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}
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}
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cmd = segment->buf[byte];
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}
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/* Send stop on last byte, if desired */
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if (send_stop && byte == segment->len - 1)
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cmd |= CMD_DATA_STOP;
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write32(®s->cmd_data, cmd);
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if (segment->flags & I2C_M_RD) {
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/* Read op only: Wait for FIFO data and store it */
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while (!(read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "I2C receive timeout\n");
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return -1;
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}
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}
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segment->buf[byte] = read32(®s->cmd_data);
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}
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return 0;
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}
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int dw_i2c_transfer(unsigned int bus,
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const struct i2c_msg *segments, size_t count)
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{
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struct stopwatch sw;
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struct dw_i2c_regs *regs;
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size_t byte;
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int ret = -1;
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if (count == 0 || !segments)
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return -1;
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regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
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if (!regs) {
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printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
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return -1;
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}
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dw_i2c_enable(regs);
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if (dw_i2c_wait_for_bus_idle(regs)) {
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printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
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goto out;
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}
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/* Process each segment */
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while (count--) {
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if (IS_ENABLED(CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG)) {
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printk(BIOS_DEBUG, "i2c %u:%02x %s %d bytes : ",
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bus, segments->slave,
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(segments->flags & I2C_M_RD) ? "R" : "W",
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segments->len);
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}
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/* Set target slave address */
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write32(®s->target_addr, segments->slave);
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/* Read or write each byte in segment */
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for (byte = 0; byte < segments->len; byte++) {
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/*
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* Set stop condition on final segment only.
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* Repeated start will be automatically generated
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* by the controller on R->W or W->R switch.
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*/
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if (dw_i2c_transfer_byte(regs, segments, byte,
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count == 0) < 0) {
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printk(BIOS_ERR, "I2C %s failed: bus %u "
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"addr 0x%02x\n",
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(segments->flags & I2C_M_RD) ?
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"read" : "write", bus, segments->slave);
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goto out;
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}
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}
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if (IS_ENABLED(CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG)) {
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int j;
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for (j = 0; j < segments->len; j++)
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printk(BIOS_DEBUG, "%02x ", segments->buf[j]);
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printk(BIOS_DEBUG, "\n");
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}
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segments++;
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}
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/* Wait for interrupt status to indicate transfer is complete */
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stopwatch_init_usecs_expire(&sw, DW_I2C_TIMEOUT_US);
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while (!(read32(®s->raw_intr_stat) & INTR_STAT_STOP_DET)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR, "I2C stop bit not received\n");
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goto out;
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}
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}
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/* Read to clear INTR_STAT_STOP_DET */
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read32(®s->clear_stop_det_intr);
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|
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/* Wait for the bus to go idle */
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if (dw_i2c_wait_for_bus_idle(regs)) {
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printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
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goto out;
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}
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/* Flush the RX FIFO in case it is not empty */
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stopwatch_init_usecs_expire(&sw, 16 * DW_I2C_TIMEOUT_US);
|
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while (read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY) {
|
||||
if (stopwatch_expired(&sw)) {
|
||||
printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n");
|
||||
goto out;
|
||||
}
|
||||
read32(®s->cmd_data);
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
|
||||
out:
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||||
read32(®s->clear_intr);
|
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dw_i2c_disable(regs);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Global I2C bus handler, defined in include/device/i2c_simple.h */
|
||||
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *msg, int count)
|
||||
{
|
||||
return dw_i2c_transfer(bus, msg, count < 0 ? 0 : count);
|
||||
}
|
||||
|
||||
static int dw_i2c_set_speed_config(unsigned int bus,
|
||||
const struct dw_i2c_speed_config *config)
|
||||
{
|
||||
struct dw_i2c_regs *regs;
|
||||
void *hcnt_reg, *lcnt_reg;
|
||||
|
||||
regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
|
||||
if (!regs || !config)
|
||||
return -1;
|
||||
|
||||
/* Nothing to do if no values are set */
|
||||
if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold)
|
||||
return 0;
|
||||
|
||||
if (config->speed >= I2C_SPEED_HIGH) {
|
||||
/* High and Fast Ultra speed */
|
||||
hcnt_reg = ®s->hs_scl_hcnt;
|
||||
lcnt_reg = ®s->hs_scl_lcnt;
|
||||
} else if (config->speed >= I2C_SPEED_FAST) {
|
||||
/* Fast and Fast-Plus speed */
|
||||
hcnt_reg = ®s->fs_scl_hcnt;
|
||||
lcnt_reg = ®s->fs_scl_lcnt;
|
||||
} else {
|
||||
/* Standard speed */
|
||||
hcnt_reg = ®s->ss_scl_hcnt;
|
||||
lcnt_reg = ®s->ss_scl_lcnt;
|
||||
}
|
||||
|
||||
/* SCL count must be set after the speed is selected */
|
||||
if (config->scl_hcnt)
|
||||
write32(hcnt_reg, config->scl_hcnt);
|
||||
if (config->scl_lcnt)
|
||||
write32(lcnt_reg, config->scl_lcnt);
|
||||
|
||||
/* Set SDA Hold Time register */
|
||||
if (config->sda_hold)
|
||||
write32(®s->sda_hold, config->sda_hold);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_i2c_gen_config_rise_fall_time(struct dw_i2c_regs *regs,
|
||||
enum i2c_speed speed,
|
||||
const struct dw_i2c_bus_config *bcfg,
|
||||
int ic_clk,
|
||||
struct dw_i2c_speed_config *config)
|
||||
{
|
||||
const struct i2c_descriptor *bus;
|
||||
const struct soc_clock *soc;
|
||||
int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt, spk_cnt;
|
||||
int hcnt, lcnt, period_cnt, diff, tot;
|
||||
int data_hold_time_ns;
|
||||
|
||||
bus = get_bus_descriptor(speed);
|
||||
soc = get_soc_descriptor(ic_clk);
|
||||
|
||||
if (bus == NULL) {
|
||||
printk(BIOS_ERR, "dw_i2c: invalid bus speed %d\n", speed);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (soc == NULL) {
|
||||
printk(BIOS_ERR, "dw_i2c: invalid SoC clock speed %d MHz\n",
|
||||
ic_clk);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Get the proper spike suppression count based on target speed. */
|
||||
if (speed >= I2C_SPEED_HIGH)
|
||||
spk_cnt = read32(®s->hs_spklen);
|
||||
else
|
||||
spk_cnt = read32(®s->fs_spklen);
|
||||
|
||||
/* Find the period, rise, fall, min tlow, and min thigh in terms of
|
||||
* counts of SoC clock. */
|
||||
period_cnt = counts_from_freq(&soc->freq, &bus->freq);
|
||||
rise_cnt = counts_from_time(&soc->freq, bcfg->rise_time_ns);
|
||||
fall_cnt = counts_from_time(&soc->freq, bcfg->fall_time_ns);
|
||||
min_tlow_cnt = counts_from_time(&soc->freq, bus->min_tlow_ns);
|
||||
min_thigh_cnt = counts_from_time(&soc->freq, bus->min_thigh_ns);
|
||||
|
||||
printk(DW_I2C_DEBUG, "dw_i2c: SoC %d/%d ns Bus: %d/%d ns\n",
|
||||
soc->freq.ticks, soc->freq.ns, bus->freq.ticks, bus->freq.ns);
|
||||
printk(DW_I2C_DEBUG,
|
||||
" dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
|
||||
period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
|
||||
spk_cnt);
|
||||
|
||||
/*
|
||||
* Back solve for hcnt and lcnt according to the following equations.
|
||||
* SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
|
||||
* SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
|
||||
*/
|
||||
hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
|
||||
lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
|
||||
|
||||
if (hcnt < 0 || lcnt < 0) {
|
||||
printk(BIOS_ERR, "dw_i2c: bad counts. hcnt = %d lcnt = %d\n",
|
||||
hcnt, lcnt);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Now add things back up to ensure the period is hit. If off,
|
||||
* split the difference and bias to lcnt for remainder. */
|
||||
tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
|
||||
|
||||
if (tot < period_cnt) {
|
||||
diff = (period_cnt - tot) / 2;
|
||||
hcnt += diff;
|
||||
lcnt += diff;
|
||||
tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
|
||||
lcnt += period_cnt - tot;
|
||||
}
|
||||
|
||||
config->speed = speed;
|
||||
config->scl_lcnt = lcnt;
|
||||
config->scl_hcnt = hcnt;
|
||||
|
||||
/* Use internal default unless other value is specified. */
|
||||
data_hold_time_ns = DEFAULT_SDA_HOLD_TIME;
|
||||
if (bcfg->data_hold_time_ns)
|
||||
data_hold_time_ns = bcfg->data_hold_time_ns;
|
||||
|
||||
config->sda_hold = counts_from_time(&soc->freq, data_hold_time_ns);
|
||||
|
||||
printk(DW_I2C_DEBUG, "dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n",
|
||||
hcnt, lcnt, config->sda_hold);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dw_i2c_gen_speed_config(uintptr_t dw_i2c_addr,
|
||||
enum i2c_speed speed,
|
||||
const struct dw_i2c_bus_config *bcfg,
|
||||
struct dw_i2c_speed_config *config)
|
||||
{
|
||||
const int ic_clk = CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ;
|
||||
struct dw_i2c_regs *regs;
|
||||
uint16_t hcnt_min, lcnt_min;
|
||||
int i;
|
||||
|
||||
regs = (struct dw_i2c_regs *)dw_i2c_addr;
|
||||
|
||||
_Static_assert(CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ != 0,
|
||||
"DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ can't be zero!");
|
||||
|
||||
/* Apply board specific override for this speed if found */
|
||||
for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) {
|
||||
if (bcfg->speed_config[i].speed != speed)
|
||||
continue;
|
||||
memcpy(config, &bcfg->speed_config[i], sizeof(*config));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* If rise time is set use the time calculation. */
|
||||
if (bcfg->rise_time_ns)
|
||||
return dw_i2c_gen_config_rise_fall_time(regs, speed, bcfg,
|
||||
ic_clk, config);
|
||||
|
||||
if (speed >= I2C_SPEED_HIGH) {
|
||||
/* High speed */
|
||||
hcnt_min = MIN_HS_SCL_HIGHTIME;
|
||||
lcnt_min = MIN_HS_SCL_LOWTIME;
|
||||
} else if (speed >= I2C_SPEED_FAST_PLUS) {
|
||||
/* Fast-Plus speed */
|
||||
hcnt_min = MIN_FP_SCL_HIGHTIME;
|
||||
lcnt_min = MIN_FP_SCL_LOWTIME;
|
||||
} else if (speed >= I2C_SPEED_FAST) {
|
||||
/* Fast speed */
|
||||
hcnt_min = MIN_FS_SCL_HIGHTIME;
|
||||
lcnt_min = MIN_FS_SCL_LOWTIME;
|
||||
} else {
|
||||
/* Standard speed */
|
||||
hcnt_min = MIN_SS_SCL_HIGHTIME;
|
||||
lcnt_min = MIN_SS_SCL_LOWTIME;
|
||||
}
|
||||
|
||||
config->speed = speed;
|
||||
config->scl_hcnt = ic_clk * hcnt_min / KHz;
|
||||
config->scl_lcnt = ic_clk * lcnt_min / KHz;
|
||||
config->sda_hold = ic_clk * DEFAULT_SDA_HOLD_TIME / KHz;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed,
|
||||
const struct dw_i2c_bus_config *bcfg)
|
||||
{
|
||||
struct dw_i2c_regs *regs;
|
||||
struct dw_i2c_speed_config config;
|
||||
uint32_t control;
|
||||
|
||||
/* Clock must be provided by Kconfig */
|
||||
regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
|
||||
if (!regs || !speed)
|
||||
return -1;
|
||||
|
||||
control = read32(®s->control);
|
||||
control &= ~CONTROL_SPEED_MASK;
|
||||
|
||||
if (speed >= I2C_SPEED_HIGH) {
|
||||
/* High and Fast-Ultra speed share config registers */
|
||||
control |= CONTROL_SPEED_HS;
|
||||
} else if (speed >= I2C_SPEED_FAST) {
|
||||
/* Fast speed and Fast-Plus */
|
||||
control |= CONTROL_SPEED_FS;
|
||||
} else {
|
||||
/* Standard speed */
|
||||
control |= CONTROL_SPEED_SS;
|
||||
}
|
||||
|
||||
/* Generate speed config based on clock */
|
||||
if (dw_i2c_gen_speed_config((uintptr_t)regs, speed, bcfg, &config) < 0)
|
||||
return -1;
|
||||
|
||||
/* Select this speed in the control register */
|
||||
write32(®s->control, control);
|
||||
|
||||
/* Write the speed config that was generated earlier */
|
||||
dw_i2c_set_speed_config(bus, &config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize this bus controller and set the speed.
|
||||
*
|
||||
* The bus speed can be passed in Hz or using values from device/i2c.h and
|
||||
* will default to I2C_SPEED_FAST if it is not provided.
|
||||
*/
|
||||
int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg)
|
||||
{
|
||||
struct dw_i2c_regs *regs;
|
||||
enum i2c_speed speed;
|
||||
|
||||
if (!bcfg)
|
||||
return -1;
|
||||
|
||||
speed = bcfg->speed ? : I2C_SPEED_FAST;
|
||||
|
||||
regs = (struct dw_i2c_regs *)dw_i2c_base_address(bus);
|
||||
if (!regs) {
|
||||
printk(BIOS_ERR, "I2C bus %u base address not found\n", bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (dw_i2c_disable(regs) < 0) {
|
||||
printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Put controller in master mode with restart enabled */
|
||||
write32(®s->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE |
|
||||
CONTROL_RESTART_ENABLE);
|
||||
|
||||
/* Set bus speed to FAST by default */
|
||||
if (dw_i2c_set_speed(bus, speed, bcfg) < 0) {
|
||||
printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Set RX/TX thresholds to smallest values */
|
||||
write32(®s->rx_thresh, 0);
|
||||
write32(®s->tx_thresh, 0);
|
||||
|
||||
/* Enable stop detection interrupt */
|
||||
write32(®s->intr_mask, INTR_STAT_STOP_DET);
|
||||
|
||||
printk(BIOS_INFO, "DW I2C bus %u at 0x%p (%u KHz)\n",
|
||||
bus, regs, speed / KHz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user