Add support for the Intel EP80579 (Tolapai) Development Kit mainboard
(Truxton). Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ed Swierk
197
src/mainboard/intel/truxton/mptable.c
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197
src/mainboard/intel/truxton/mptable.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "Intel ";
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static const char productid[12] = "Truxton ";
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struct mp_config_table *mc;
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u8 bus_num;
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u8 bus_isa;
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u8 bus_pea0 = 0;
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u8 bus_pea1 = 0;
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u8 bus_aioc;
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device_t dev;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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memcpy(mc->mpc_signature, sig, sizeof(sig));
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_spec = 0x04;
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mc->mpc_checksum = 0; /* not yet computed */
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memcpy(mc->mpc_oem, oem, sizeof(oem));
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memcpy(mc->mpc_productid, productid, sizeof(productid));
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_lapic = LAPIC_ADDR;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc);
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/* AIOC bridge */
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dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
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if (dev) {
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bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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}
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else {
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printk_debug("ERROR - could not find PCI 0:04.0\n");
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bus_aioc = 0;
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bus_isa = 9;
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}
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/* PCIe A0 */
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dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI 0:02.0\n");
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bus_pea0 = 0;
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}
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/* PCIe A1 */
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dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
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if (dev) {
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bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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printk_debug("ERROR - could not find PCI 0:03.0\n");
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bus_pea1 = 0;
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}
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/* IOAPIC handling */
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smp_write_ioapic(mc, 0x8, 0x20, 0xfec00000);
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/* ISA backward compatibility interrupts */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x8, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x8, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x8, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x8, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x8, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x8, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
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bus_isa, 0x08, 0x8, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x8, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x8, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x8, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x8, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x8, 0x0f);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* IMCH/IICH PCI devices */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
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if (bus_pea0) {
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/* PCIe slot 0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea0, (0<<2)|0, 0x8, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea0, (0<<2)|1, 0x8, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea0, (0<<2)|2, 0x8, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea0, (0<<2)|3, 0x8, 0x13);
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}
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if (bus_pea1) {
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/* PCIe slots 1-4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea1, (0<<2)|0, 0x8, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea1, (0<<2)|1, 0x8, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea1, (0<<2)|2, 0x8, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_pea1, (0<<2)|3, 0x8, 0x13);
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}
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if (bus_aioc) {
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/* AIOC PCI devices */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
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}
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk_debug("Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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