soc/intel/tigerlake: Update TCSS for SW CM support
This change adds support for SW CM. Add Operating System Capabilities (_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet Protocol tunneling and enable PCIe tunneling as well. Remove Connect Topology(CNTP) command because kernel driver directly works with SW CM Thunderbolt firmware. Update _DSD method for USB4 support across XHCI and PCIe root ports. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao
Tim Wawrzynczak
parent
277e11b390
commit
b8febf44d1
@ -29,9 +29,19 @@
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#define MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE 0x00000015
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#define TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS 0 /* Sub-command 0 */
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#define TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ 1 /* Sub-command 1 */
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#define TCSS_IOM_ACK_TIMEOUT_IN_MS 100
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#define MCHBAR_TCSS_DEVEN_OFFSET 0x7090
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#define REVISION_ID 1
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#define UNRECOGNIZED_UUID 0x4
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#define UNRECOGNIZED_REVISION 0x8
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#define USB_TUNNELING 0x1
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#define DISPLAY_PORT_TUNNELING 0x2
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#define PCIE_TUNNELING 0x4
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#define INTER_DOMAIN_USB4_INTERNET_PROTOCOL 0x8
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Scope (\_SB)
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{
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/* Device base address */
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@ -126,6 +136,46 @@ Scope (\_SB)
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}
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Return (0)
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}
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Method (_OSC, 4, Serialized)
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{
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/*
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* Operating System Capabilities for USB4
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* Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A}
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* Arg1: Revision ID = 1
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* Arg2: Count of entries (DWORD) in Arg3 (Integer): 3
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* Arg3: DWORD capabilities buffer:
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* First DWORD: The standard definition bits are used to return errors.
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* Second DWORD: OSPM support field for USB4, bits [31:0] reserved.
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* Third DWORD: OSPM control field for USB4.
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* bit 0: USB tunneling
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* bit 1: DisplayPort tunneling
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* bit 2: PCIe tunneling
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* bit 3: Inter-domain USB4 internet protocol
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* bit 31:4: reserved
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* Return: The platform acknowledges the capabilities buffer by returning
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* a buffer of DWORD of the same length. Masked/Cleared bits in the
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* control field indicate that the platform does not permit OSPM
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* control of the respectively capabilities or features.
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*/
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Name (CTRL, 0) /* Control field value */
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If (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) {
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CreateDWordField(Arg3, 0, CDW1)
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CreateDWordField(Arg3, 2, CDW3)
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CTRL = CDW3
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If (Arg1 != REVISION_ID) {
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CDW1 |= UNRECOGNIZED_REVISION
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}
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CTRL |= USB_TUNNELING | DISPLAY_PORT_TUNNELING | PCIE_TUNNELING |
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INTER_DOMAIN_USB4_INTERNET_PROTOCOL
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CDW3 = CTRL
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Return (Arg3)
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} Else {
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CDW1 |= UNRECOGNIZED_UUID
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Return (Arg3)
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}
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}
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}
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Scope (_GPE)
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@ -251,6 +301,25 @@ Scope (_GPE)
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Scope (\_SB.PCI0)
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{
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/*
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* Operation region defined to access the TCSS_DEVEN. Get the MCHBAR in offset
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* 0x48 in B0:D0:F0. TCSS device enable base address is in offset 0x7090 of MCHBAR.
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*/
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OperationRegion (TDEN, SystemMemory, (GMHB() + MCHBAR_TCSS_DEVEN_OFFSET), 0x4)
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Field (TDEN, ByteAcc, NoLock, Preserve)
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{
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TRE0, 1, /* PCIE0_EN */
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TRE1, 1, /* PCIE1_EN */
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TRE2, 1, /* PCIE2_EN */
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TRE3, 1, /* PCIE3_EN */
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, 4,
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THCE, 1, /* XHCI_EN */
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TDCE, 1, /* XDCI_EN */
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DME0, 1, /* TBT_DMA0_EN */
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DME1, 1, /* TBT_DMA1_EN */
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, 20
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}
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/*
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* Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset
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* 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR.
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@ -423,17 +492,6 @@ Scope (\_SB.PCI0)
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IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
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}
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/*
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* Below is a variable to store devices connect state for TBT PCIe RP before
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* entering D3 cold.
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* Value 0 - no device connected before enter D3 cold, no need to send
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* CONNECT_TOPOLOGY in D3 cold exit.
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* Value 1 - has device connected before enter D3 cold, need to send
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* CONNECT_TOPOLOGY in D3 cold exit.
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*/
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Name (CTP0, 0) /* Variable of device connecet status for TBT0 group. */
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Name (CTP1, 0) /* Variable of device connecet status for TBT1 group. */
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/*
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* TBT Group0 ON method
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*/
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@ -455,28 +513,6 @@ Scope (\_SB.PCI0)
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/* RP1 D3 cold exit. */
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\_SB.PCI0.TRP1.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM0.ALCT == 1) {
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If (CTP0 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM0.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM0.WACT = 1
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/* Clear the connect states. */
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CTP0 = 0
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}
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/* Disallow to send Connect-Topology command. */
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\_SB.PCI0.TDM0.ALCT = 0
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}
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} Else {
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Printf("Drop TG0N due to it is already exit D3 cold.")
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}
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@ -500,16 +536,10 @@ Scope (\_SB.PCI0)
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP0.PDSX == 1) {
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CTP0 = 1
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}
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/* Put RP0 to D3 cold. */
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\_SB.PCI0.TRP0.D3CE()
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}
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If (\_SB.PCI0.TRP1.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP1.PDSX == 1) {
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CTP0 = 1
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}
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/* Put RP1 to D3 cold. */
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\_SB.PCI0.TRP1.D3CE()
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}
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@ -538,28 +568,6 @@ Scope (\_SB.PCI0)
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/* RP3 D3 cold exit. */
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\_SB.PCI0.TRP3.D3CX()
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}
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/*
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* Need to send Connect-Topology command when TBT host
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* controller back to D0 from D3.
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*/
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If (\_SB.PCI0.TDM1.ALCT == 1) {
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If (CTP1 == 1) {
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/*
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* Send Connect-Topology command if there is
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* device present on PCIe RP.
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*/
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\_SB.PCI0.TDM1.CNTP()
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/* Indicate to wait Connect-Topology command. */
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\_SB.PCI0.TDM1.WACT = 1
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/* Clear the connect states. */
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CTP1 = 0
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}
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/* Disallow to send Connect-Topology cmd. */
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\_SB.PCI0.TDM1.ALCT = 0
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}
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} Else {
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Printf("Drop TG1N due to it is already exit D3 cold.")
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}
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@ -583,16 +591,10 @@ Scope (\_SB.PCI0)
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Printf("Push TBT RPs to D3Cold together")
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If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP2.PDSX == 1) {
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CTP1 = 1
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}
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/* Put RP2 to D3 cold. */
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\_SB.PCI0.TRP2.D3CE()
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}
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If (\_SB.PCI0.TRP3.VDID != 0xFFFFFFFF) {
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If (\_SB.PCI0.TRP3.PDSX == 1) {
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CTP1 = 1
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}
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/* Put RP3 to D3 cold */
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\_SB.PCI0.TRP3.D3CE()
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}
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@ -763,7 +765,11 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (THCE == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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#include "tcss_xhci.asl"
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}
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@ -781,7 +787,11 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (DME0 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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#include "tcss_dma.asl"
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}
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@ -799,7 +809,11 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (DME1 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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#include "tcss_dma.asl"
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}
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@ -818,8 +832,13 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (TRE0 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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Method (_INI)
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{
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LTEN = 0
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@ -843,8 +862,13 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (TRE1 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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Method (_INI)
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{
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LTEN = 0
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@ -868,8 +892,13 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (TRE2 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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Method (_INI)
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{
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LTEN = 0
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@ -893,8 +922,13 @@ Scope (\_SB.PCI0)
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Method (_STA, 0x0, NotSerialized)
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{
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If (TRE3 == 1) {
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Return (0x0F)
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} Else {
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Return (0x0)
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}
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}
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Method (_INI)
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{
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LTEN = 0
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@ -26,118 +26,7 @@ Field (DPME, AnyAcc, NoLock, Preserve)
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DMAD, 8 /* 31:24 DMA Active Delay */
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}
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/*
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* TBT MailBox Command Method
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* Arg0 - MailBox Cmd ID
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*/
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Method (ITMB, 1, Serialized)
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{
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Local0 = Arg0 | 0x1 /* 0x1, PCIE2TBT_VLD_B */
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P2TB = Local0
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}
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/*
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* Wait For Command Completed
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* Arg0 - TimeOut value (unit is 1 millisecond)
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*/
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Method (WFCC, 1, Serialized)
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{
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WTBS (Arg0)
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P2TB = 0
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WTBC (Arg0)
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}
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/*
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* Wait For Command Set
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* Arg0 - TimeOut value
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*/
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Method (WTBS, 1, Serialized)
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{
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Local0 = Arg0
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While (Local0 > 0) {
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/* Wait for Bit to Set. */
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If (TB2P & 0x1) { /* 0x1, TBT2PCIE_DON_R */
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Break
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}
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Local0--
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Sleep (1)
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}
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}
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/*
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* Wait For Command Clear
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* Arg0 - TimeOut value
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*/
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Method (WTBC, 1, Serialized)
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{
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Local0 = Arg0
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While (Local0 > 0) {
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/* Wait for Bit to Clear. */
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If ((TB2P & 0x1) != 0x0) { /* 0x1, TBT2PCIE_DON_R */
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Break
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}
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Local0--
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Sleep (1)
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}
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}
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/*
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* TCSS TBT CONNECT_TOPOLOGY MailBox Command Method
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*/
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Method (CNTP, 0, Serialized)
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{
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Local0 = 0
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/* Set Force Power if it is not set */
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If (DFPE == 0) {
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DMAD = 0x22
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DFPE = 1
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/*
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* Poll the TBT NVM FW Ready bit with timeout(default is 500ms) before
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* send the TBT MailBox command.
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*/
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While ((INFR == 0) && (Local0 < 500)) {
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Sleep (1)
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Local0++
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}
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}
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If (Local0 != 100) {
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ITMB (0x3E) /* 0x3E, PCIE2TBT_CONNECT_TOPOLOGY_COMMAND */
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}
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}
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Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
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Name (ALCT, 0x0) /* Connect-Topology cmd can be sent or not 1 - yes, 0 - no */
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/*
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* Wait Connect-Topology cmd done
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* 0 - no need to wait
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* 1 - need to wait
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* 2 - wait in progress
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*/
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Name (WACT, 0x0)
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Method (_PS0, 0, Serialized)
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{
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If (WACT == 1) {
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/*
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* PCIe rp0/rp1 is grouped with DMA0 and PCIe rp2/rp3 is grouped wit DMA1.
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* Whenever the Connect-Topology command is in the process, WACT flag is set 1.
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* PCIe root ports 0/1/2/3/ and DMA 0/1 _PS0 method set WACT to 2 to indicate
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* other thread's _PS0 to wait for the command completion. WACT is cleared to
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* be 0 after command is finished.
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*/
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WACT = 2
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WFCC (100) /* Wait for command complete. */
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WACT = 0
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} ElseIf (WACT == 2) {
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While (WACT != 0) {
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Sleep (5)
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}
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}
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}
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Method (_PS3, 0, Serialized)
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{
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}
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Method (_S0W, 0x0)
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{
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@ -178,7 +67,6 @@ Method (D3CE, 0, Serialized)
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{
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DD3E = 1 /* Enable DMA RTD3 */
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STAT = 0
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ALCT = 0x1 /* Allow to send Connect-Topology cmd. */
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}
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/*
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@ -195,34 +195,8 @@ Method (_PS0, 0, Serialized)
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If (PMEX == 1) {
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PMEX = 0 /* Disable Power Management SCI */
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}
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Sleep(100) /* Wait for 100ms before return to OS starts any DS activities. */
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If ((TUID == 0) || (TUID == 1)) {
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If (\_SB.PCI0.TDM0.WACT == 1) {
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/*
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* Indicate other thread's _PS0 to wait the response.
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*/
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\_SB.PCI0.TDM0.WACT = 2
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\_SB.PCI0.TDM0.WFCC (10) /* Wait for command complete. */
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\_SB.PCI0.TDM0.WACT = 0
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} ElseIf (\_SB.PCI0.TDM0.WACT == 2) {
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While (\_SB.PCI0.TDM0.WACT != 0) {
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Sleep (5)
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}
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}
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} Else {
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If (\_SB.PCI0.TDM1.WACT == 1) {
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/*
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* Indicate other thread's _PS0 to wait the response.
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*/
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\_SB.PCI0.TDM1.WACT = 2
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\_SB.PCI0.TDM1.WFCC (10) /* Wait for command complete. */
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\_SB.PCI0.TDM1.WACT = 0
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} ElseIf (\_SB.PCI0.TDM1.WACT == 2) {
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While (\_SB.PCI0.TDM1.WACT != 0) {
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Sleep (5)
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}
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}
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}
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Sleep(100) /* Wait for 100ms before return to OS starts any OS activities. */
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}
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Method (_PS3, 0, Serialized)
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@ -246,8 +220,8 @@ Method (_PS3, 0, Serialized)
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}
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Method (_DSD, 0) {
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Return (
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Package () {
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If ((TUID == 0) || (TUID == 1)) {
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Return ( Package() {
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/* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */
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ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
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Package ()
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@ -264,9 +238,64 @@ Method (_DSD, 0) {
|
||||
* (NumOfTBTRP - 1).
|
||||
*/
|
||||
Package (2) { "UID", TUID },
|
||||
},
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 },
|
||||
Package (2) { "usb4-port-number", TUID },
|
||||
}
|
||||
})
|
||||
} ElseIf (TUID == 2) {
|
||||
Return ( Package () {
|
||||
/* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */
|
||||
ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "HotPlugSupportInD3", 1 },
|
||||
},
|
||||
|
||||
/* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */
|
||||
ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"),
|
||||
Package () {
|
||||
Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */
|
||||
/*
|
||||
* UID of the TBT RP on platform, range is: 0, 1 ...,
|
||||
* (NumOfTBTRP - 1).
|
||||
*/
|
||||
Package (2) { "UID", TUID },
|
||||
},
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 0 },
|
||||
}
|
||||
})
|
||||
} Else { /* TUID == 3 */
|
||||
Return ( Package () {
|
||||
/* acpi_pci_bridge_d3 at ../drivers/pci/pci-acpi.c */
|
||||
ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "HotPlugSupportInD3", 1 },
|
||||
},
|
||||
|
||||
/* pci_acpi_set_untrusted at ../drivers/pci/pci-acpi.c */
|
||||
ToUUID("EFCC06CC-73AC-4BC3-BFF0-76143807C389"),
|
||||
Package () {
|
||||
Package (2) { "ExternalFacingPort", 1 }, /* TBT/CIO port */
|
||||
/*
|
||||
* UID of the TBT RP on platform, range is: 0, 1 ...,
|
||||
* (NumOfTBTRP - 1).
|
||||
*/
|
||||
Package (2) { "UID", TUID },
|
||||
},
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package () {
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 1 },
|
||||
}
|
||||
})
|
||||
}
|
||||
)
|
||||
}
|
||||
|
||||
Method (_S0W, 0x0, NotSerialized)
|
||||
|
||||
@ -118,20 +118,68 @@ Device (RHUB)
|
||||
Device (SS01)
|
||||
{
|
||||
Name (_ADR, 0x02)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 },
|
||||
Package (2) { "usb4-port-number", 0 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS02)
|
||||
{
|
||||
Name (_ADR, 0x03)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM0 },
|
||||
Package (2) { "usb4-port-number", 1 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS03)
|
||||
{
|
||||
Name (_ADR, 0x04)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 0 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
Device (SS04)
|
||||
{
|
||||
Name (_ADR, 0x05)
|
||||
Method (_DSD, 0, NotSerialized)
|
||||
{
|
||||
Return( Package ()
|
||||
{
|
||||
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package (2) { "usb4-host-interface", \_SB.PCI0.TDM1 },
|
||||
Package (2) { "usb4-port-number", 1 }
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user