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mb/system76/gaze17: switch to S3

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Change-Id: I65d4dc008addceb95d5f37758b98f243b2a290dd
This commit is contained in:
Jeremy Soller
2023-03-07 07:16:18 -07:00
parent 26918833dd
commit b950bd1cd8
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/system76/gaze17/Kconfig
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@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select EC_SYSTEM76_EC select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU select EC_SYSTEM76_EC_DGPU
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
@ -20,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_HOTPLUG select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_ALDERLAKE_S3
select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG select SOC_INTEL_CRASHLOG
select SPD_READ_BY_WORD select SPD_READ_BY_WORD

2
src/mainboard/system76/gaze17/devicetree.cb
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@ -12,8 +12,6 @@ chip soc/intel/alderlake
# Enable Enhanced Intel SpeedStep # Enable Enhanced Intel SpeedStep
register "eist_enable" = "1" register "eist_enable" = "1"
register "s0ix_enable" = "1"
# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c) # FSP Memory (soc/intel/alderlake/romstage/fsp_params.c)
# Enable C6 DRAM # Enable C6 DRAM
register "enable_c6dram" = "1" register "enable_c6dram" = "1"