soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -67,8 +67,6 @@ void fch_early_init(void)
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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lpc_disable_spi_rom_sharing();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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espi_clear_decodes();
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espi_setup();
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espi_setup();
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}
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}
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}
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@ -100,13 +100,6 @@ int espi_open_io_window(uint16_t base, size_t size);
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*/
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*/
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int espi_open_mmio_window(uint32_t base, size_t size);
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int espi_open_mmio_window(uint32_t base, size_t size);
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/*
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* Clear all configured eSPI memory and I/O decode ranges. This is useful for changing
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* the decodes, or if something else has previously setup decode windows that conflict
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* with the windows that coreboot needs.
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*/
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void espi_clear_decodes(void);
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/*
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/*
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* In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
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* In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
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* SPIBASE. This is required for cases where verstage runs on PSP.
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* SPIBASE. This is required for cases where verstage runs on PSP.
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@ -98,7 +98,7 @@ static int espi_get_unused_io_window(void)
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return -1;
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return -1;
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}
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}
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void espi_clear_decodes(void)
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static void espi_clear_decodes(void)
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{
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{
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unsigned int idx;
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unsigned int idx;
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@ -894,6 +894,7 @@ int espi_setup(void)
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espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
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espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
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espi_write32(ESPI_SLAVE0_INT_EN, 0);
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espi_write32(ESPI_SLAVE0_INT_EN, 0);
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espi_clear_status();
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espi_clear_status();
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espi_clear_decodes();
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/*
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/*
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* Boot sequence: Step 1
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* Boot sequence: Step 1
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