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AGESA: Drop unused assembly files

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Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14396
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
2016-04-18 12:09:00 +03:00
parent 6de9795143
commit b97dc871d9
75 changed files with 0 additions and 56597 deletions
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383
src/vendorcode/amd/agesa/f10/Legacy/PlatformMemoryConfiguration.inc
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; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
;
; ****************************************************************************
; *
; * Copyright (c) 2011, Advanced Micro Devices, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; * * Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; * * Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
; * its contributors may be used to endorse or promote products derived
; * from this software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 4
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 6
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 3
DB SocketID
DB ChannelID
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 3
DB SocketID
DB ChannelID
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 3
DB SocketID
DB ANY_CHANNEL
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 10
DB SocketID
DB ChannelID
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 6
DB SocketID
DB ANY_CHANNEL
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 11
DB SocketID
DB ChannelID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 3
DB ANY_SOCKET
DB ANY_CHANNEL
DB 1
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************

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src/vendorcode/amd/agesa/f10/Legacy/Proc/arch2008.asm
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src/vendorcode/amd/agesa/f10/Legacy/agesa.inc
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src/vendorcode/amd/agesa/f10/Legacy/amd.inc
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; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
; *
; * Copyright (c) 2011, Advanced Micro Devices, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; * * Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; * * Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
; * its contributors may be used to endorse or promote products derived
; * from this software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_LATE_RUN_AP_TASK EQU 00020010h
AMD_IDENTIFY_DIMMS EQU 00020011h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

577
src/vendorcode/amd/agesa/f10/Legacy/bridge32.inc
View File

@ -1,577 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

624
src/vendorcode/amd/agesa/f10/Lib/IA32/amdlib32.asm
View File

@ -1,624 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo8
WriteIo8 PROC NEAR C USES DX AX Address:WORD, Data:Byte
mov dx, Address
mov al, Data
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo16
WriteIo16 PROC NEAR C USES DX AX Address:WORD, Data:WORD
mov dx, Address
mov ax, Data
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo32
WriteIo32 PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
mov dx, Address
mov eax, Data
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] - IO port address
; * @retval IO port Value
; */
public ReadIo8
ReadIo8 PROC NEAR C USES DX Address:WORD
mov dx, Address
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] Address IO port address
; * @retval IO port Value
; */
public ReadIo16
ReadIo16 PROC NEAR C USES DX Address:WORD
mov dx, Address
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] Address IO port address
; * @retval IO port Value
; */
public ReadIo32
ReadIo32 PROC NEAR C USES DX Address:WORD
mov dx, Address
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] Address MSR Address
; * @param[in] Data Pointer to data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdMsrRead
LibAmdMsrRead PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov ecx, Address
rdmsr
mov esi, Value
mov [esi], eax
mov [esi+4], edx
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] Address MSR Address
; * @param[in] Data Pointer to data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdMsrWrite
LibAmdMsrWrite PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov ecx, Address
mov esi, Data
mov eax, [esi]
mov edx, [esi+4]
wrmsr
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] Func CPUID function
; * @param[in] DATA Pointer to CPUID_DATA to save cpuid data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdCpuidRead
LibAmdCpuidRead PROC NEAR C Func:DWORD, DATA:PTR, ConfigPtr:PTR
pushad
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov eax, Func
cpuid
mov esi, DATA
mov [esi], eax
mov [esi+4], ebx
mov [esi+8], ecx
mov [esi+12],edx
popad
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; *
; */
public ReadTSC
ReadTSC PROC NEAR C
rdtsc
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Set FS_BASE
; *
; *
; *
; * @param[in] esi - Low Dword of physical address
; * @param[in] edi - High Dword of physical address
; */
SetFsBase PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
mov eax, ecx
mov ecx, 0C0010015h ; HWCR
rdmsr
mov ebx, eax
bts eax, 17 ; HWCR.Wrap32Dis
wrmsr
xchg edx, edi
mov eax, esi
mov esi, ebx
mov ecx, 0C0000100h ; FS_BASE
wrmsr
ret
SetFsBase ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Restore MSR0C001_0015
; *
; * @param[in] esi - Low Dword
; * @param[in] edi - High Dword
; */
RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
mov ecx, 0C0010015h
mov eax, esi
mov edx, edi
wrmsr
ret
RestoreHwcr ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] Address - Memory Address
; * @retval Memory byte at given address
; */
Read64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov al, fs:[ebx]
call RestoreHwcr
jmp Done
AccesBelow4G:
mov al, ds:[esi]
Done:
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] Address - Memory Address
; * @retval Memory word at given address
; */
Read64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov ax, fs:[ebx]
call RestoreHwcr
jmp Done
AccesBelow4G:
mov ax, ds:[esi]
Done:
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] Address - Memory Address
; * @retval Memory dword at given address
; */
Read64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov eax, fs:[ebx]
call RestoreHwcr
jmp Done
AccesBelow4G:
mov eax, ds:[esi]
Done:
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:BYTE
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov al, Data
mov fs:[ebx], al
call RestoreHwcr
jmp Done
AccesBelow4G:
mov al, Data
mov ds:[esi], al
Done:
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:WORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov ax, Data
mov fs:[ebx], ax
call RestoreHwcr
jmp Done
AccesBelow4G:
mov ax, Data
mov ds:[esi], ax
Done:
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI FS Address:QWORD, Data:DWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
call SetFsBase
xor ebx, ebx
mov eax, Data
mov fs:[ebx], eax
call RestoreHwcr
jmp Done
AccesBelow4G:
mov eax, Data
mov ds:[esi], eax
Done:
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] Value Value to write
; */
LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
pushad
push ds
.if(Reg == 00h)
mov eax, cr0
.elseif(Reg == 04h)
mov eax, cr4
.elseif(Reg == 10h)
mov eax, dr0
.elseif(Reg == 11h)
mov eax, dr1
.elseif(Reg == 12h)
mov eax, dr2
.elseif(Reg == 13h)
mov eax, dr3
.elseif(Reg == 17h)
mov eax, dr7
.else
xor eax,eax
.endif
mov edi, Value
mov [edi], eax
pop ds
popad
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] Value Value to write
; */
LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
mov eax, Value
.if(Reg == 00h)
mov cr0, eax
.elseif(Reg == 4)
mov cr4, eax
.elseif(Reg == 10h)
mov dr0, eax
.elseif(Reg == 11h)
mov dr1, eax
.elseif(Reg == 12h)
mov dr2, eax
.elseif(Reg == 13h)
mov dr3, eax
.elseif(Reg == 17h)
mov dr7, eax
.endif
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC NEAR C
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC NEAR C
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC NEAR C
pushad
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popad
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] Address IO Port Address
; * @param[in] Value Value to write
; * @param[in] Flag IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
push edx
push eax
push ebx
mov edx, Address
mov eax, Value
mov ebx, Flag
out dx, eax
pop ebx
pop eax
pop edx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC NEAR C
pushad
mov ecx, 0C001100Ah ;bit 0 = HDT redirect
mov edi, 09C5A203Ah ;Password
RDMSR ;
or al, 1 ;
WRMSR ;
mov al, 0B2h ;Marker = B2
db 0F1h ;ICEBP
popad
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with .
; *
; * @param[in] Value Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC NEAR C Value:DWORD
mov eax, Value
bsf eax, Value
.if (Zero?)
mov al,32
.endif
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] Value Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC NEAR C Value:DWORD
mov eax, Value
bsr eax, Value
.if (Zero?)
mov al,0FFh
.endif
ret
LibAmdBitScanReverse ENDP
END

110
src/vendorcode/amd/agesa/f10/Lib/IA32/ms_shift.asm
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@ -1,110 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the right.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_aullshr PROC NEAR C PUBLIC
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov eax, edx
xor edx, edx
.endif
shrd eax, edx, cl
shr edx, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_aullshr ENDP
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the left.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_allshl PROC NEAR C PUBLIC USES CX
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov edx, eax
xor eax, eax
.endif
shld edx, eax, cl
shl eax, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_allshl ENDP
END

84
src/vendorcode/amd/agesa/f10/Lib/IA32/msmemcpy.asm
View File

@ -1,84 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
; void *memcpy( void *dest, void *src, size_t count );
;
; Copy count bytes from src to dest, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memcpy
memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov esi, src
mov ecx, count
rep movsb
mov eax, dest
popf
ret
memcpy ENDP
; void *memset( void *dest, int c, size_t count );
;
; At dest, set count bytes to byte value, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memset
memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov eax, value
mov ecx, count
rep stosb
mov eax, edi
popf
ret
memset ENDP
END

569
src/vendorcode/amd/agesa/f10/Lib/x64/amdlib64.asm
View File

@ -1,569 +0,0 @@
;/**
; * @file
; *
; * Agesa library 64bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.code
;/*++
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] CX IO port address
; * @param[in] DL IO port Value
; */
PUBLIC WriteIo8
WriteIo8 PROC
mov al, dl
mov dx, cx
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] CX IO port address
; * @param[in] DX IO port Value
; */
PUBLIC WriteIo16
WriteIo16 PROC
mov ax, dx
mov dx, cx
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] CX IO port address
; * @param[in] EDX IO port Value
; */
PUBLIC WriteIo32
WriteIo32 PROC
mov eax, edx
mov dx, cx
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] CX IO port address
; * @retval AL IO port Value
; */
PUBLIC ReadIo8
ReadIo8 PROC
mov dx, cx
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] CX IO port address
; * @retval AX IO port Value
; */
PUBLIC ReadIo16
ReadIo16 PROC
mov dx, cx
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] CX IO port address
; * @retval EAX IO port Value
; */
PUBLIC ReadIo32
ReadIo32 PROC
mov dx, cx
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrRead
LibAmdMsrRead PROC
push rsi
mov rsi, rdx
rdmsr
mov [rsi], eax
mov [rsi+4], edx
pop rsi
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrWrite
LibAmdMsrWrite PROC
push rsi
mov rsi, rdx
mov eax, [rsi]
and rax, 0ffffffffh
mov edx, [rsi+4]
and rdx, 0ffffffffh
wrmsr
pop rsi
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] RCX CPUID function
; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdCpuidRead
LibAmdCpuidRead PROC
push rbx
push rsi
mov rsi, rdx
mov rax, rcx
cpuid
mov [rsi], eax
mov [rsi+4], ebx
mov [rsi+8], ecx
mov [rsi+12],edx
pop rsi
pop rbx
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; * @retval RAX Time stamp counter value
; */
PUBLIC ReadTSC
ReadTSC PROC
rdtsc
and rax, 0ffffffffh
shl rdx, 32
or rax, rdx
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] RCX - Memory Address
; * @retval Memory byte at given address
; */
PUBLIC Read64Mem8
Read64Mem8 PROC
xor rax, rax
mov al, [rcx]
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] RCX - Memory Address
; * @retval Memory word at given address
; */
PUBLIC Read64Mem16
Read64Mem16 PROC
xor rax, rax
mov ax, [rcx]
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] RCX - Memory Address
; * @retval Memory dword at given address
; */
PUBLIC Read64Mem32
Read64Mem32 PROC
xor rax, rax
mov eax, [rcx]
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] RCX Memory Address
; * @param[in] DL Value to write
; */
PUBLIC Write64Mem8
Write64Mem8 PROC
xor rax, rax
mov rax, rdx
mov [rcx], al
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] RCX Memory Address
; * @param[in] DX Value to write
; */
PUBLIC Write64Mem16
Write64Mem16 PROC
xor rax, rax
mov rax, rdx
mov [rcx], ax
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] RCX Memory Address
; * @param[in] EDX Value to write
; */
PUBLIC Write64Mem32
Write64Mem32 PROC
xor rax, rax
mov rax, rdx
mov [rcx], eax
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Pointer to value
; */
PUBLIC LibAmdReadCpuReg
LibAmdReadCpuReg PROC
push rax
xor rax, rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
jmp RegRead
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
jmp RegRead
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
jmp RegRead
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
jmp RegRead
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
jmp RegRead
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
jmp RegRead
Reg17h:
cmp cl, 17h
jne RegRead
mov rax, dr7
RegRead:
mov [rdx], eax
pop rax
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Value to write
; */
PUBLIC LibAmdWriteCpuReg
LibAmdWriteCpuReg PROC
push rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
mov eax, edx
mov cr0, rax
jmp Done
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
mov eax, edx
mov cr4, rax
jmp Done
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
mov eax, edx
mov dr0, rax
jmp Done
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
mov eax, edx
mov dr1, rax
jmp Done
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
mov eax, edx
mov dr2, rax
jmp Done
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
mov eax, edx
mov dr3, rax
jmp Done
Reg17h:
cmp cl, 17h
jne Done
mov rax, dr7
mov eax, edx
mov dr7, rax
Done:
pop rax
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC
pushfq
mov rax, 0BACCD00Bh ; Backdoor in SimNow
mov rbx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popfq
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] ECX IO Port Address
; * @param[in] EDX Value to write
; * @param[in] R8D IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC
push rbx
push rax
mov ebx, r8d
mov eax, edx
mov edx, ecx
out dx, eax
pop rax
pop rbx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC
push rbx
mov rcx, 0C001100Ah ;bit 0 = HDT redirect
mov rdi, 09C5A203Ah ;Password
rdmsr
and rax, 0ffffffffh
or rax, 1
wrmsr
mov rax, 0B2h ;Marker = B2
db 0F1h ;ICEBP
pop rbx
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC
bsf eax, ecx
jnz nonZeroSource
mov al,32
nonZeroSource:
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC
bsr eax, ecx
jnz nonZeroSource
mov al,0FFh
nonZeroSource:
ret
LibAmdBitScanReverse ENDP
END

113
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
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@ -1,113 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; PciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
mov ecx, 0C001001Fh
rdmsr
push eax
push ecx
push edx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, PciRegister
mov edx, PciAddress
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dx, 0CF8h ; Set Reg Config Space
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax ; move data to return position
db 0Fh, 0AEh, 0F0h ; MFENCE
pop edx
pop ecx
pop eax
wrmsr
ret
F10RevDProbeFilterCritical ENDP
END

127
src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
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@ -1,127 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; PciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC F10RevDProbeFilterCritical
F10RevDProbeFilterCritical PROC
push rax
push rcx
push rdx
push rsi
push rdi
mov esi, ecx
mov edi, edx
mov ecx, 0C001001Fh
rdmsr
push rax
push rcx
push rdx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, edi
mov edx, esi
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
mfence
mov dx, 0CF8h ; Set Reg Config Space
mfence
out dx, eax
mfence
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
mfence
out dx, eax ; move data to return position
mfence
pop rdx
pop rcx
pop rax
wrmsr
pop rdi
pop rsi
pop rdx
pop rcx
pop rax
ret
F10RevDProbeFilterCritical ENDP
END

319
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
View File

@ -1,319 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE agesa.inc
INCLUDE cpcarmac.inc
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y A B S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; ExecuteFinalHltInstruction: Disables the stack and performs
; a hlt instruction on an AP.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteFinalHltInstruction PROC NEAR C PUBLIC
pop esi ; StdHeader
pop esi ; pointer to ApMtrrSettingsList, set through build configuration
mov eax, CR0 ; Make sure cache is disabled for all APs
or eax, CR0_CD OR CR0_NW ; Disable cache
mov cr0, eax ; Write back to CR0
; Configure the MTRRs on the AP so
; when it runs remote code it will execute
; out of RAM instead of ROM.
; Disable MTRRs and turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MtrrVarDramEn ; Disable
bts eax, MtrrFixDramModEn ; Enable
btr eax, MtrrFixDramEn ; Disable
bts eax, SysUcLockEn
_WRMSR
; Setup default values for Fixed-Sized MTRRs
; Set 7FFFh-00000h as WB
mov ecx, AMD_AP_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR
; Set 9FFFFh-80000h also as WB
mov ecx, AMD_AP_MTRR_FIX16k_80000
_WRMSR
; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
mov ecx, AMD_AP_MTRR_FIX16k_A0000
xor eax, eax
xor edx, edx
_WRMSR
; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
xor eax, eax
xor edx, edx
mov ecx, AMD_AP_MTRR_FIX4k_C0000
CDLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_D8000
jbe CDLoop
; Set FFFFFh-E0000h as Uncacheable Memory
mov eax, 18181818h
mov edx, eax
mov ecx, AMD_AP_MTRR_FIX4k_E0000
EFLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_F8000
jbe EFLoop
; If IBV provided settings for Fixed-Sized MTRRs,
; overwrite the default settings.
.if (esi != 0)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
; While we are not at the end of the list
.while (ecx != CPU_LIST_TERMINAL)
; Ensure that the MSR address is valid for Fixed-Sized MTRRs
.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
_WRMSR
.endif
add esi, sizeof (AP_MTRR_SETTINGS)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
.endw
.endif
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
.while (cl < 010h)
_WRMSR
inc cl
.endw
; Enable fixed-range and variable-range MTRRs
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
or ax, 0C00h ; Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
_WRMSR
; Enable Top-of-Memory setting
; Enable use of RdMem/WrMem bits attributes
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MtrrVarDramEn ; Enable
btr eax, MtrrFixDramModEn ; Disable
bts eax, MtrrFixDramEn ; Enable
_WRMSR
; Enable the self modifying code check buffer and Enable hardware prefetches
mov ecx, 0C0011022h
_RDMSR
btr eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads bit
btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
btr eax, DIS_HW_PF ; Disable hardware prefetches bit
_WRMSR
dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
_RDMSR
btr eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable L3 cache to accept clear lines
xor eax, eax
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteHltInstruction PROC NEAR C PUBLIC
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
NmiHandler PROC NEAR C PUBLIC
iretd
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
GetCsSelector PROC NEAR C PUBLIC, CsSelector:PTR
push ax
push ebx
call FarCallGetCs
mov ebx, CsSelector
mov [ebx], ax
pop ebx
pop ax
ret
GetCsSelector ENDP
;======================================================================
; FarCallGetCs:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
; WARNING: This routine has a mirror routine in the PREMEM segment.
; These two routines MUST be sync'd for content.
;======================================================================
FarCallGetCs PROC FAR PRIVATE
mov ax, ss:[esp + 4]
retf
FarCallGetCs ENDP
;======================================================================
; SetIdtr:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
; WARNING: This routine has a mirror routine in the PREMEM segment.
; These two routines MUST be sync'd for content.
;======================================================================
SetIdtr PROC NEAR C PUBLIC USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
lidt fword ptr ss:[ebx]
ret
SetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
ExecuteWbinvdInstruction PROC NEAR C PUBLIC
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

138
src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib32.asm
View File

@ -1,138 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 32bit
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 14305 $ @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
public IdsDelay
IdsDelay PROC NEAR C USES EAX EDX
Local targetedx:dword, targeteax:dword
rdtsc
;set target time
add eax,1500000000
adc edx,0
mov targetedx,edx
mov targeteax,eax
rdtsc
;set "Si!=0" skip below loop
.while(1)
.if(si != 0)
jmp delay_exit
.endif
.if(edx > targetedx)
jmp delay_exit
.elseif (edx == targetedx)
.if(eax > targeteax)
jmp delay_exit
.endif
.endif
rdtsc
.endw
delay_exit:
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC NEAR C filecode:dword
local tmpebx:dword,tmpedx:dword
pushad
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, filecode
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov ebx,0dead0000h
mov edx,filecode
ror edx,16
mov bx,dx
mov dx,0
;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
mov tmpebx,ebx
mov tmpedx,edx
xor eax,eax
mov cl,6
.while((cl != 0) && (si == 0))
.if(cl <= 2)
shld eax,edx,8
shl edx,8
.else
shld eax,ebx,8
shl ebx,8
.endif
out 80h,eax
call IdsDelay
dec cl
.if(cl == 0)
mov cl,6
mov ebx,tmpebx
mov edx,tmpedx
.endif
.endw
popad
xor eax,eax
ret
IdsErrorStop endp
END

143
src/vendorcode/amd/agesa/f10/Proc/IDS/Control/IdsLib64.asm
View File

@ -1,143 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 64bit
; *
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 14126 $ @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.code
IdsDelay PROC
push rax
push rdx
push rbx
xor rax,rax
xor rdx,rdx
rdtsc
;set target time
add eax,1500000000
adc edx,0
shl rdx,32
add rdx,rax
mov rbx,rdx
;rbx store the target
;set "Si!=0" skip below loop
__loop:
cmp si,0
jnz __loopexit
rdtsc
shl rdx,32
add rdx,rax
cmp rdx,rbx
jae __loopexit
jmp __loop
__loopexit:
pop rbx
pop rdx
pop rax
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC
;As x64 calling convention RCX is used as input parameters
push rcx
push rbx
push si
push dx
push rbx
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, ecx
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov rax,0dead00000000h
or rcx,rax
;rcx= 0dead__FILECODE
shl rcx,16
;rcx= 0dead__FILECODE__0000
mov rbx,rcx
xor rax,rax
mov dl,6
IdsErrorStopLoop:
cmp dl,0
jz IdsErrorStopExit
cmp si,0
jnz IdsErrorStopExit
shld rax,rcx,8
shl rcx,8
out 80h,eax
call IdsDelay
dec dl
cmp dl,0
jnz _nextloop
mov dl,6
mov rcx,rbx
_nextloop:
jmp IdsErrorStopLoop
IdsErrorStopExit:
pop rbx
pop dx
pop si
pop rbx
pop rcx
xor rax,rax
ret
IdsErrorStop endp
END

483
src/vendorcode/amd/agesa/f10/Proc/Mem/Main/mu.asm
View File

@ -1,483 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
; Description: Main memory controller system configuration for AGESA
;
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;memUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written
;
; Out:
;
; All registers preserved.
;===============================================================================
MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemUOutPort ENDP
;----------------------------------------------------------------------------
; _SFENCE();
;
_SFENCE macro
db 0Fh,0AEh,0F8h
endm
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemUWriteCachelines:
; Write a test pattern to DRAM
;
; In: Pattern - pointer to the write pattern
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
xor ecx, ecx
mov cx,ClCount
shl ecx,2
@@:
db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemUWriteCachelines ENDP
;===============================================================================
;MemUReadCachelines:
;
; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
;pattern is a stress pattern which exercises both ISI and crosstalk. The number
;of cache lines to fill is dependent on DCT width mode and burstlength.
;
; In: Buffer - pointer to a buffer where read data will be stored
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL Count:BYTE
pushad
; First, issue continuous dummy reads to fill up the cache
mov eax,Address
.if (ClCount > 18)
mov cx,ClCount
shr cx,4
mov Count,cl
.while (Count != 0)
push eax
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
pop eax
add eax,(16*64) ;Next 16CL
dec Count
.endw
.else
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
.if(ClCount == 1)
_MFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
.elseif(ClCount == 3)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
.elseif(ClCount == 6)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
.elseif(ClCount == 9)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
.elseif(ClCount == 18)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
mov eax,fs:[edx] ;TestAddr+16 cache lines
_MFENCE
mov eax,fs:[edx+64] ;TestAddr+17 cache lines
_MFENCE
.endif
.endif
_MFENCE
; Then, copy data to buffer
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
xor ecx, ecx
mov cx,ClCount
shl ecx,6
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemUReadCachelines ENDP
;===============================================================================
;MemUDummyCLRead:
;
; Perform a single cache line read from a given physical address.
;
; In: Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
_SFENCE
pushad
mov eax,Address
mov dl,fs:[eax]
popad
ret
MemUDummyCLRead ENDP
;===============================================================================
;MemUFlushPattern:
;
; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
;to ensure cache miss on the next read training.
;
; In: Address - Physical address to be flushed
; ClCount - number of cachelines to be flushed
; Out:
;
;All registers preserved.
;===============================================================================
MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
pushad
mov edi,Address
movzx ecx,ClCount
@@:
_MFENCE ; Force strong ordering of clflush
db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
_MFENCE
add edi,64
loop @B
popad
ret
MemUFlushPattern ENDP
;===============================================================================
;MemUGetWrLvNblErr:
; Read ClCount number of cachelines then return the bitmap that indicates
; the write leveling result of each byte lane.
;
; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
; Address - Physical address to be sampled
; ClCount - number of cachelines to be read
;
; OUT: ErrBitmap - WL result
;
;All registers preserved
;===============================================================================
MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL ZeroCount[32]:WORD
pushad
mov esi,Address
_EXECFENCE
;Cache fill
movzx ecx,ClCount
@@:
mov eax,fs:[esi]
add esi,64
loop @B
_MFENCE
; Then, count the number of 0's
;push es
;push ss
;pop es
lea edi,ZeroCount
mov cx,SIZEOF ZeroCount
mov al,0
rep stosb
;pop es
mov esi,Address
lea edi,ZeroCount
mov cx,ClCount
shl cx,6
.while(cx > 0)
mov al,fs:[esi]
test al,00Fh ;check lower nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
test al,0F0h ;check upper nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
inc esi
dec cx
test cx,07h
.if(ZERO?)
sub edi,(16*2)
sub cx,8
add esi,8
.endif
.endw
; Then, average and compress data to error bits
lea esi,ZeroCount
mov dx,ClCount
shl dx,1
xor eax,eax
xor ecx,ecx
mov cl,0
.while(cl<16)
.if(WORD PTR [esi] < dx)
bts eax,ecx
.endif
add esi,2
inc cl
.endw
xor edx,edx
mov dx,WORD PTR ErrBitmap
mov [edx], ax
popad
ret
MemUGetWrLvNblErr ENDP
;===============================================================================
;AlignPointerTo16Byte:
; Modifies BufferPtr to be 16 byte aligned
;
; In: BufferPtrPtr - Pointer to buffer pointer
; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
;
;All registers preserved.
;===============================================================================
AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
push edx
push eax
mov edx, BufferPtrPtr
mov eax, [edx]
add eax, 16
and ax, 0FFF0h
mov [edx], eax
pop eax
pop edx
ret
AlignPointerTo16Byte ENDP
END

187
src/vendorcode/amd/agesa/f10/Proc/Recovery/Mem/mru.asm
View File

@ -1,187 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
; Description: Main memory controller system configuration for AGESA DDR 2
;
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;MemRecUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written to port
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemRecUOutPort ENDP
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemRecUWrite1CL:
;
; Write data from buffer to a system address
;
; In: Address - System address to read from
; Pattern - pointer pattern.
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
mov ecx,4
@@:
db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemRecUWrite1CL ENDP
;===============================================================================
;MemRecURead1CL:
;
; Read one cacheline to buffer
;
; In: Buffer - pointer buffer.
; : Address - System address to read from
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
pushad
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
mov ecx,64
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemRecURead1CL ENDP
;===============================================================================
;MemRecUFlushPattern:
;
; Flush one cache line
;
; In: Address - System address [31:0]
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
pushad
mov eax,Address
_EXECFENCE
;clflush fs:[eax]
db 064h ;access relative to FS BASE prefix
db 00Fh ;opcode
db 0AEh ;opcode
db 038h ;eax indirect addressing
_MFENCE
popad
ret
MemRecUFlushPattern ENDP
END

406
src/vendorcode/amd/agesa/f10/cpcarmac.inc
View File

@ -1,406 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Workfile: cpcarmac.inc $Revision:: 44323 $ $Date:: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; none
;
; Out:
; SS:ESP - Our new private stack location
; 4000:3FFC - for BSP (16K Stack)
; 4000:7FFC - for core0 of node1 (16K Stack)
; 4000:BFFC - for core0 of node2 (16K Stack)
; 4000:FFFC - for core0 of node3 (16K Stack)
; 5000:3FFC - for core0 of node4 (16K Stack)
; 5000:7FFC - for core0 of node5 (16K Stack)
; 5000:BFFC - for core0 of node6 (16K Stack)
; 5000:FFFC - for core0 of node7 (16K Stack)
;
; 6000:1FFC - for core1 node0 (4k stack)
; 6000:2FFC - for core2 node0 (4k stack)
; ...
; 9000:8FFC - for core7 of node7 (4k stack) ......... max of 64 cores in system
;
; EAX = AGESA_STATUS
;
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processors
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es
;
;======================================================================
AMD_ENABLE_STACK MACRO
local SetupStack
local SetupDramMap
local get_SS_ESP
local r16bmode
local p32mode
local init_stack
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
mov esp, ebx ; put return address in a safe place
; get node id and core id of current executing core
mov si, -1
GET_NODE_ID_CORE_ID
movzx edi, di
; determine if stack is already enabled.
mov eax, cr0
test eax, 60000000h
jnz SetupStack
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
test ah, 0Ch
jz SetupStack
or edi, 0FFFF0000h ; indicate stack has already been initialized
jmp get_SS_ESP
SetupStack:
; Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
mov eax, 8000C06Ch
mov dx, 0CF8h
out dx, eax
add dx, 4
in eax, dx
btr eax, 0
out dx, eax
; Setup temporary DRAM map for CAS on all nodes
mov eax, 8000C060h ; Get NodeCnt from BSP
mov dx, 0CF8h
out dx, eax
add dx, 4
in al, dx
shr ax, 4
and al, 7
mov cl, al
mov ebx, 8000C144h
SetupDramMap:
mov eax, ebx ; Set 0000_0000 to 00FF_FFFF as DRAM
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 0
out dx, eax
mov eax, ebx
sub eax, 4
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 3
out dx, eax
add bh, 8
dec cl
jns SetupDramMap
; Disable the self modifying code check buffer and Disable hardware prefetches
mov ecx, 0C0011022h
_RDMSR
bts eax, DC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
bts eax, DIS_CLR_WBTOL2_SMC_HIT ; turn on Disable the self modifying code check buffer bit
bts eax, DIS_HW_PF ; turn on Disable hardware prefetches bit
_WRMSR
dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
_RDMSR
bts eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
_WRMSR
AMD_ENABLE_STACK_FAMILY_HOOK ; Disable L3 cache to accept clear lines
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
and eax, 0FFE3FFFFh ; turn off MTRR enable bits
bts eax, MtrrFixDramModEn ; turn on modification enable bit
_WRMSR
; clear all variable and Fixed MTRRs
mov ecx, 200h
xor eax, eax
xor edx, edx
.while (cl != 10h) ; MTRRphysBasen and MTRRphysMaskn
_WRMSR
inc cl
.endw
mov cl, 50h ; MTRRfix64K_00000
_WRMSR
mov cl, 58h ; MTRRfix16K_80000
_WRMSR
mov cl, 59h ; MTRRfix16K_A0000
_WRMSR
mov cl, 68h ; MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; setup MTRR for stacks
mov ebx, WB_DRAM_TYPE
.if (di == 0) ;core 0
.if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h
shl ebx, 8
.endif
mov ecx, AMD_MTRR_FIX64k_00000
_RDMSR
or edx, ebx
_WRMSR
.else ;core 1 to core 7 start at 60000h
.if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR
shl ebx, 16
.if (si > 1)
shl ebx, 8
.endif
mov ecx, AMD_MTRR_FIX64k_00000
_RDMSR
or edx, ebx
_WRMSR
.else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR
mov ecx, AMD_MTRR_FIX16k_80000
_RDMSR
.if (si < 6) ; node 4 and node 5
.if (si == 4) ; node 4
.if (di >= 4)
shl ebx, 8
.endif
.else ; node 5
shl ebx, 16
.if (di >= 4)
shl ebx, 8
.endif
.endif
or eax, ebx
_WRMSR
.else ; node 6 and node 7
.if (si == 6) ; node 6
.if (di >= 4)
shl ebx, 8
.endif
.else ; node 7
shl ebx, 16
.if (di >= 4)
shl ebx, 8
.endif
.endif
or edx, ebx
_WRMSR
.endif
.endif
.endif
; Clear IORRs, TOP_MEM and TOM2
xor eax, eax
xor edx, edx
mov ecx, 0C0010016h ;IORRBase0
.while (cl != 1Bh)
_WRMSR
inc cl
.endw
mov cl, 1Dh
_WRMSR
; Enable MTRRs
mov ecx, 02FFh ; MTRRdefType
mov ah, 0Ch ; MtrrDefTypeEn and MtrrDefTypeFixEn
_WRMSR
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MtrrFixDramEn ; MtrrFixDramEn
btr eax, MtrrFixDramModEn ; turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, 31 ; make sure paging is disabled
btr eax, 30 ; Clear CR0 NW and CD
btr eax, 29
mov CR0, eax
get_SS_ESP:
; allocate space for stacks
xor cx, cx
xor edx, edx
.if (di == 0) ;core 0
mov eax, CORE0_STACK_BASE_ADDR
.while (cx <= si)
add eax, 4000h
inc cx
.endw
mov edx, eax
sub eax, 4000h
and eax, 0F0000h
sub edx, 4
and edx, 0FFFFh
mov bx, CORE0_STACK_SIZE / 4
.else ;core 1 to core 7 start at 60000h
mov eax, CORE1_STACK_BASE_ADDR ; core 1 stack starts at 60000h
.while (cx <= si)
add eax, 8000h ; 32k for each node
inc cx
.endw
sub eax, 8000h
mov dx, ax
and eax, 0F0000h
xor cx, cx
.while (cx <= di)
add edx, 1000h ; 4k for APs
inc cx
.endw
sub edx, 4
mov bx, CORE1_STACK_SIZE / 4
.endif
; Allocate stack and set ESP
mov ecx, CR0 ; check for 32-bit protect mode
test ecx, 1 ; PE bit
jz r16bmode ; PE=0, real mode
mov cx, cs ; PE=1
cmp cx, 0D000h ; check for CS
jb p32mode ; if CS < D000, it is a selector instead of a segment
r16bmode:
shr eax, 4 ; ax = ss, ds, es
mov ss, ax
mov ds, ax
mov es, ax
jmp init_stack
p32mode:
add edx, eax ; linear address of the stack
init_stack:
.if ( !(edi & 0FFFF0000h))
std
xor ecx, ecx
mov cx, bx
mov esi, edx
rep lods DWORD PTR [esi]
xor eax, eax
mov cx, bx
mov edi, edx
rep stos DWORD PTR [edi]
cld
xor eax, eax ; eax = 0 : no error
.else
mov eax, 40000001h ; eax = AGESA_WARNING (Stack has already been set up)
.endif
mov cx, bx ; ecx = size in dwords
shl ecx, 2 ; ecx = size in bytes
mov ebx, esp
mov esp, edx
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_STATUS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; save return address
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MtrrFixDramModEn ; Enable
_WRMSR
; Disable MTRRs and turn on modification enable bit
mov ecx,AMD_MTRR_FIX64k_00000
mov eax,1E1E1E1Eh
mov edx,eax
_WRMSR ; 0 - 512K = WB Mem
mov cl,58h
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MtrrFixDramModEn ; Disable
_WRMSR
; Enable the self modifying code check buffer and Enable hardware prefetches
mov ecx, 0C0011022h
_RDMSR
btr eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads bit
btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable the self modifying code check buffer bit
btr eax, DIS_HW_PF ; Disable hardware prefetches bit
_WRMSR
dec cx ; MSRC001_1021 Instruction Cache Configuration Register (IC_CFG)
_RDMSR
btr eax, IC_DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable L3 cache to accept clear lines
mov ebx, esp
xor eax, eax
ENDM

420
src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc
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@ -1,420 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
;
; ****************************************************************************
; *
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 4
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 6
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 3
DB SocketID
DB ChannelID
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 3
DB SocketID
DB ChannelID
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 3
DB SocketID
DB ANY_CHANNEL
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 10
DB SocketID
DB ChannelID
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 6
DB SocketID
DB ANY_CHANNEL
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 11
DB SocketID
DB ChannelID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 20
DB SocketID
DB ChannelID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 3
DB SocketID
DB ChannelID
DB 1
ENDM
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
DB 3
DB SocketID
DB ChannelID
DB 1
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 3
DB ANY_SOCKET
DB ANY_CHANNEL
DB 1
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************

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src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm
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src/vendorcode/amd/agesa/f12/Legacy/agesa.inc
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src/vendorcode/amd/agesa/f12/Legacy/amd.inc
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; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
; *
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

576
src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc
View File

@ -1,576 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

452
src/vendorcode/amd/agesa/f12/cpcarmac.inc
View File

@ -1,452 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Workfile: cpcarmac.inc $Revision:: 44324 $ $Date:: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
.mmx
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; EBX = Return address (preserved)
;
; Out:
; SS:ESP - Our new private stack location
;
; EAX = AGESA_STATUS
; EDX = Return status code if EAX contains a return code of higher
; severity than AGESA_SUCCESS
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processor cores
; Preserved:
; ebx ebp
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es, ss, esp
; mmx0, mmx1
;
; Description:
; Fixed MTRR address allocation to cores:
; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
; There is a max of 1 BSP, 7 core0s and 56 other cores.
; Although each core has it's own cache storage, they share the address space. Each core must
; be assigned a private and unique address space for its stack. To support legacy systems,
; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
;
; 80000h 40000h 00000h
; +----------+----------+----------+----------+----------+----------+----------+----------+
; 64K | | | | | | | | | 64K ea
; ea +----------+----------+----------+----------+----------+----------+----------+----------+
; | MTRR 0000_0250 MTRRfix64K_00000 |
; +----------+----------+----------+----------+----------+----------+----------+----------+
; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
; +----------+----------+----------+----------+----------+----------+----------+----------+
;
; C0000h B0000h A0000h 90000h 80000h
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;16K | | | | | | | | | | | | | | | | |
; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;
; E0000h D0000h C0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;
; 100000h F0000h E0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;======================================================================
AMD_ENABLE_STACK MACRO
local AmdEnableStackExit
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
movd mm0, ebx ; Put return address in a safe place
movd mm1, ebp ; Save some other user registers
; get node id and core id of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
; If we detected an unknown processor family or core combination, return AGESA_FATAL.
.if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.endif
; determine if stack is already enabled. We are using the DefType MSR for this determination.
; It is =0 after reset; CAR setup sets it to enable the MTRRs
mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
.if (!(eax & CR0_MASK))
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
.if (eax & MSR_MASK)
bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
.endif
.endif
; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
mov ebx, esi ; Get my Node/Core info
xor bl, bl
shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
add ah, bh
mov ebx, eax ; Save PCI address for Base/Limit pair
mov dx, 0CF8h
out dx, eax
add dx, 4
xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
out dx, eax ; DRAM Limit = node0, no interleave
mov eax, ebx
sub eax, 4 ; Now point to the Base register
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 00000003h ; Set the read and write enable bits
out dx, eax ; DRAM Base = 0x0000, R/W
AMD_ENABLE_STACK_FAMILY_HOOK
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
_WRMSR
mov eax, esi
bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
.if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
.if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
; Clear all variable and Fixed MTRRs for non-shared cores
mov ecx, AMD_MTRR_VARIABLE_BASE0
xor eax, eax
xor edx, edx
.while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
_WRMSR
inc cl
.endw
mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
_WRMSR
mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
_WRMSR
mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
_WRMSR
mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
; - not strictly needed since the FixedMTRRs take presedence.
mov eax, (16 * 1024 * 1024)
mov ecx, TOP_MEM ; MSR:C001_001A
_WRMSR
.endif ; End Is_Primary
.endif ; End Stack_ReEntry
; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor eax, eax
xor edx, edx
mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
.while (cl != 1Ah)
_WRMSR
inc cl
.endw
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
; To prevent speculative reads from causing an eviction, the unused cache ranges are set
; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
; Note: some core stack regions will share an MTRR since the control granularity is much
; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
; space covered by the MTRR when parseling out cache space for the various uses. In some cases
; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
;
; Outcome of this block is that: (Note the MTRR map at the top of the file)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
;
mov ax, si ; Load node, core
.if (al == 0) ; Is a core 0?
.if (ah == 0) ; Is Node 0? (BSP)
; Is BSP, assign a 64K stack
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE / 1000h))
mov ebp, BSP_STACK_BASE_ADDR
.else ; node 1 to 7, core0
; Is a Core0 of secondary node, assign 16K stacks
mov bx, AMD_MTRR_FIX16k_80000
shl ebx, 16 ;
mov bh, ah ; Node# is used as slot#
mov bl, (CORE0_STACK_SIZE / 1000h)
mov al, ah ; Base = (Node# * Size);
mul bl ;
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE0_STACK_BASE_ADDR
mov ebp, eax
.endif
.else ;core 1 thru core 7
; Is core 1-7 of any node, assign 4K stacks
mov al, 8 ; CoreIndex = ( (Node# * 8) ...
mul ah ;
mov bx, si ;
add al, bl ; ... + Core#);
mov bx, AMD_MTRR_FIX64k_00000
shl ebx, 16 ;
mov bh, al ; Slot# = (CoreIndex / 16) + 4;
shr bh, 4 ;
add bh, 4 ;
mov bl, (CORE1_STACK_SIZE / 1000h)
mul bl ; Base = ( (CoreIndex * Size) ...
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
mov ebp, eax
.endif
; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
mov cl, bh ; ShiftCount = ((slot# ...
and cl, 03h ; ... % 4) ...
shl cl, 3 ; ... * 8);
shl edi, cl ; Cache type is now in correct position
ror ebx, 16 ; Get the MTRR address
movzx ecx, bx ;
rol ebx, 16 ; Put slot# & size back in BX
_RDMSR ; Read-modify-write the MSR
.if (bh < 4) ; Is value in lower or upper half of MSR?
or eax, edi ;
.else ;
or edx, edi ;
.endif ;
_WRMSR ;
; Enable MTRR defaults as UC type
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Read-modify-write the MSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Close the modification window on the Fixed MTRRs
mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, CR0_PG ; Make sure paging is disabled
btr eax, CR0_CD ; Clear CR0 NW and CD
btr eax, CR0_NW
mov CR0, eax
; Use the Stack Base & size to calculate SS and ESP values
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
;
mov esp, ebp ; Initialize the stack pointer
mov edi, esp ; Copy the stack start to edi
movzx bx, bl
movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
shl ebx, 12 ; Make size full byte count (* 4K)
add esp, ebx ; Set the Stack Pointer as full linear address
sub esp, 4
;
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - 32b start address of stack block
; ebx - size of stack block
; esp - 32b linear stack pointer
;
; Determine mode for SS base;
mov ecx, CR0 ; Check for 32-bit protect mode
bt ecx, CR0_PE ;
.if (!carry?) ; PE=0 means real mode
mov cx, cs ;
.if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
; alter SS:ESP for 16b Real Mode:
mov eax, edi ;
shr eax, 4 ; Create a Real Mode segment for ss, ds, es
mov ss, ax ;
mov ds, ax ;
mov es, ax ;
shl eax, 4 ;
sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
mov esp, ebx ; Make SP an offset from SS
sub esp, 4 ;
.endif ; endif
; else
; Default is to use Protected 32b Mode
.endif
;
; Clear The Stack
; Now that we have set the location and the MTRRs, initialize the cache by
; reading then writing to zero all of the stack area.
; review:
; ss - Stack base
; esp - stack pointer
; ebx - size of stack block
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - address of start of stack block
;
shr ebx, 2 ;
mov cx, bx ; set cx for size count of DWORDS
; Check our flags - Don't clear an existing stack
.if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
cld
mov esi, edi
rep lods DWORD PTR [esi] ; Pre-load the range
xor eax, eax
mov cx, bx
mov esi, edi ; Preserve base for push on stack
rep stos DWORD PTR [edi] ; Clear the range
mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
shl ebx, 2 ; Put stack size and base
push ebx ; in top of stack
push esi
mov ecx, ebx ; Return size of stack in bytes
mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
.else
movzx ecx, cx
shl ecx, 2 ; Return size of stack, in bytes
mov edx, CPU_EVENT_STACK_REENTRY
mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
.endif
AmdEnableStackExit:
movd ebx, mm0 ; Restore return address
movd ebp, mm1
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_SUCCESS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; Save return address
; get node/core/flags of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
_WRMSR
; Set lower 640K MTRRs for Write-Back memory caching
mov ecx, AMD_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR ; 0 - 512K = WB Mem
mov ecx, AMD_MTRR_FIX16k_80000
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
mov ebx, esp ; restore return address (ebx)
xor eax, eax
ENDM

402
src/vendorcode/amd/agesa/f14/Legacy/PlatformMemoryConfiguration.inc
View File

@ -1,402 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 4
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 6
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 3
DB SocketID
DB ChannelID
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 3
DB SocketID
DB ChannelID
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 3
DB SocketID
DB ANY_CHANNEL
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 10
DB SocketID
DB ChannelID
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 6
DB SocketID
DB ANY_CHANNEL
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 11
DB SocketID
DB ChannelID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 20
DB SocketID
DB ChannelID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 3
DB SocketID
DB ChannelID
DB 1
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************

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src/vendorcode/amd/agesa/f14/Legacy/Proc/arch2008.asm
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src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
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src/vendorcode/amd/agesa/f14/Legacy/amd.inc
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; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 33891 $ @e \$Date: 2010-06-26 00:22:54 +0800 (Sat, 26 Jun 2010) $
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

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@ -1,577 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

151
src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm
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@ -1,151 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.xmm
.model flat,C
ASSUME FS:NOTHING
.code
;---------------------------------------------------------------------------
;
; _mm_clflush_fs - execute clflush instruction for address fs:address32
; this lets clflush operate beyond 4GB in 32-bit mode
;
; void _mm_clflush_fs (void *address32);
;
_mm_clflush_fs proc public
mov eax, [esp+8]
clflush fs:[eax]
ret
_mm_clflush_fs ENDP
;---------------------------------------------------------------------------
;
; _mm_stream_si128_fs - execute movntdq instruction for address fs:address32
; this lets movntdq operate beyond 4GB in 32-bit mode
;
; void _mm_stream_si128_fs (void *dest, void *data)
;
_mm_stream_si128_fs proc public
push esi
mov esi, [esp+12]
movdqa xmm0, [esi]
mov esi, [esp+8]
movntdq fs:[esi], xmm0
pop esi
ret
_mm_stream_si128_fs ENDP
;---------------------------------------------------------------------------
END

110
src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm
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@ -1,110 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the right.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_aullshr PROC NEAR C PUBLIC
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov eax, edx
xor edx, edx
.endif
shrd eax, edx, cl
shr edx, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_aullshr ENDP
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the left.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_allshl PROC NEAR C PUBLIC USES CX
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov edx, eax
xor eax, eax
.endif
shld edx, eax, cl
shl eax, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_allshl ENDP
END

84
src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm
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@ -1,84 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
; void *memcpy( void *dest, void *src, size_t count );
;
; Copy count bytes from src to dest, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memcpy
memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov esi, src
mov ecx, count
rep movsb
mov eax, dest
popf
ret
memcpy ENDP
; void *memset( void *dest, int c, size_t count );
;
; At dest, set count bytes to byte value, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memset
memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov eax, value
mov ecx, count
rep stosb
mov eax, edi
popf
ret
memset ENDP
END

591
src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm
View File

@ -1,591 +0,0 @@
;/**
; * @file
; *
; * Agesa library 64bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.code
;/*++
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] CX IO port address
; * @param[in] DL IO port Value
; */
PUBLIC WriteIo8
WriteIo8 PROC
mov al, dl
mov dx, cx
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] CX IO port address
; * @param[in] DX IO port Value
; */
PUBLIC WriteIo16
WriteIo16 PROC
mov ax, dx
mov dx, cx
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] CX IO port address
; * @param[in] EDX IO port Value
; */
PUBLIC WriteIo32
WriteIo32 PROC
mov eax, edx
mov dx, cx
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] CX IO port address
; * @retval AL IO port Value
; */
PUBLIC ReadIo8
ReadIo8 PROC
mov dx, cx
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] CX IO port address
; * @retval AX IO port Value
; */
PUBLIC ReadIo16
ReadIo16 PROC
mov dx, cx
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] CX IO port address
; * @retval EAX IO port Value
; */
PUBLIC ReadIo32
ReadIo32 PROC
mov dx, cx
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrRead
LibAmdMsrRead PROC
push rsi
mov rsi, rdx
rdmsr
mov [rsi], eax
mov [rsi+4], edx
pop rsi
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrWrite
LibAmdMsrWrite PROC
push rsi
mov rsi, rdx
mov eax, [rsi]
and rax, 0ffffffffh
mov edx, [rsi+4]
and rdx, 0ffffffffh
wrmsr
pop rsi
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] RCX CPUID function
; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdCpuidRead
LibAmdCpuidRead PROC
push rbx
push rsi
mov rsi, rdx
mov rax, rcx
cpuid
mov [rsi], eax
mov [rsi+4], ebx
mov [rsi+8], ecx
mov [rsi+12],edx
pop rsi
pop rbx
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; * @retval RAX Time stamp counter value
; */
PUBLIC ReadTSC
ReadTSC PROC
rdtsc
and rax, 0ffffffffh
shl rdx, 32
or rax, rdx
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] RCX - Memory Address
; * @retval Memory byte at given address
; */
PUBLIC Read64Mem8
Read64Mem8 PROC
xor rax, rax
mov al, [rcx]
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] RCX - Memory Address
; * @retval Memory word at given address
; */
PUBLIC Read64Mem16
Read64Mem16 PROC
xor rax, rax
mov ax, [rcx]
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] RCX - Memory Address
; * @retval Memory dword at given address
; */
PUBLIC Read64Mem32
Read64Mem32 PROC
xor rax, rax
mov eax, [rcx]
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] RCX Memory Address
; * @param[in] DL Value to write
; */
PUBLIC Write64Mem8
Write64Mem8 PROC
xor rax, rax
mov rax, rdx
mov [rcx], al
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] RCX Memory Address
; * @param[in] DX Value to write
; */
PUBLIC Write64Mem16
Write64Mem16 PROC
xor rax, rax
mov rax, rdx
mov [rcx], ax
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] RCX Memory Address
; * @param[in] EDX Value to write
; */
PUBLIC Write64Mem32
Write64Mem32 PROC
xor rax, rax
mov rax, rdx
mov [rcx], eax
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Pointer to value
; */
PUBLIC LibAmdReadCpuReg
LibAmdReadCpuReg PROC
push rax
xor rax, rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
jmp RegRead
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
jmp RegRead
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
jmp RegRead
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
jmp RegRead
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
jmp RegRead
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
jmp RegRead
Reg17h:
cmp cl, 17h
jne RegRead
mov rax, dr7
RegRead:
mov [rdx], eax
pop rax
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Value to write
; */
PUBLIC LibAmdWriteCpuReg
LibAmdWriteCpuReg PROC
push rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
mov eax, edx
mov cr0, rax
jmp Done
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
mov eax, edx
mov cr4, rax
jmp Done
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
mov eax, edx
mov dr0, rax
jmp Done
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
mov eax, edx
mov dr1, rax
jmp Done
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
mov eax, edx
mov dr2, rax
jmp Done
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
mov eax, edx
mov dr3, rax
jmp Done
Reg17h:
cmp cl, 17h
jne Done
mov rax, dr7
mov eax, edx
mov dr7, rax
Done:
pop rax
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC
pushfq
mov rax, 0BACCD00Bh ; Backdoor in SimNow
mov rbx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popfq
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] ECX IO Port Address
; * @param[in] EDX Value to write
; * @param[in] R8D IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC
push rbx
push rax
mov ebx, r8d
mov eax, edx
mov edx, ecx
out dx, eax
pop rax
pop rbx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC
push rbx
mov rcx, 0C001100Ah ;bit 0 = HDT redirect
mov rdi, 09C5A203Ah ;Password
rdmsr
and rax, 0ffffffffh
or rax, 1
wrmsr
mov rax, 0B2h ;Marker = B2
db 0F1h ;ICEBP
pop rbx
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC
bsf eax, ecx
jnz nonZeroSource
mov al,32
nonZeroSource:
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC
bsr eax, ecx
jnz nonZeroSource
mov al,0FFh
nonZeroSource:
ret
LibAmdBitScanReverse ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Flush specified number of cache line
; *
; * @param[in] RCX Physical address to be flushed
; * @param[in] DL number of cachelines to be flushed
; */
PUBLIC LibAmdCLFlush
LibAmdCLFlush PROC
push rax
mov rax, rcx
movzx rcx, dl
@@:
mfence
clflush [rax]
mfence
add rax,64
loop @B
pop rax
ret
LibAmdCLFlush ENDP
END

113
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
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@ -1,113 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; PciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
mov ecx, 0C001001Fh
rdmsr
push eax
push ecx
push edx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, PciRegister
mov edx, PciAddress
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dx, 0CF8h ; Set Reg Config Space
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax ; move data to return position
db 0Fh, 0AEh, 0F0h ; MFENCE
pop edx
pop ecx
pop eax
wrmsr
ret
F10RevDProbeFilterCritical ENDP
END

127
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
View File

@ -1,127 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; PciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC F10RevDProbeFilterCritical
F10RevDProbeFilterCritical PROC
push rax
push rcx
push rdx
push rsi
push rdi
mov esi, ecx
mov edi, edx
mov ecx, 0C001001Fh
rdmsr
push rax
push rcx
push rdx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, edi
mov edx, esi
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
mfence
mov dx, 0CF8h ; Set Reg Config Space
mfence
out dx, eax
mfence
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
mfence
out dx, eax ; move data to return position
mfence
pop rdx
pop rcx
pop rax
wrmsr
pop rdi
pop rsi
pop rdx
pop rcx
pop rax
ret
F10RevDProbeFilterCritical ENDP
END

345
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
View File

@ -1,345 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 35270 $ @e \$Date: 2010-07-20 00:02:41 +0800 (Tue, 20 Jul 2010) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE agesa.inc
INCLUDE cpcarmac.inc
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y A B S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; ExecuteFinalHltInstruction: Disables the stack and performs
; a hlt instruction on an AP.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteFinalHltInstruction
ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
mov esi, HaltFlags
mov edi, ApMtrrSettingList
; Do these special steps in case if the core is part of a compute unit
; Note: The following bits are family specific flags, that gets set during build time,
; and indicates things like "family cache control methodology", etc.
; esi bit0 = 0 -> not a Primary core
; esi bit0 = 1 -> Primary core
; esi bit1 = 0 -> Cache disable
; esi bit1 = 1 -> Cache enable
.if (esi & 2h)
; Set CombineCr0Cd bit
mov ecx, CU_CFG3
_RDMSR
bts edx, (COMBINE_CR0_CD - 32)
_WRMSR
; Clear the CR0.CD bit
mov eax, CR0 ; Make sure cache is enabled for all APs
btr eax, CR0_CD
btr eax, CR0_NW
mov CR0, eax ; Write back to CR0
.else
mov eax, CR0 ; Make sure cache is disabled for all APs
bts eax, CR0_CD ; Disable cache
bts eax, CR0_NW
mov CR0, eax ; Write back to CR0
.endif
.if (esi & 1h)
; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
mov esi, edi ; Get ApMtrrSettingList
; Configure the MTRRs on the AP so
; when it runs remote code it will execute
; out of RAM instead of ROM.
; Disable MTRRs and turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MTRR_VAR_DRAM_EN ; Disable
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
btr eax, MTRR_FIX_DRAM_EN ; Disable
bts eax, SYS_UC_LOCK_EN
_WRMSR
; Setup default values for Fixed-Sized MTRRs
; Set 7FFFh-00000h as WB
mov ecx, AMD_AP_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR
; Set 9FFFFh-80000h also as WB
mov ecx, AMD_AP_MTRR_FIX16k_80000
_WRMSR
; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
mov ecx, AMD_AP_MTRR_FIX16k_A0000
xor eax, eax
xor edx, edx
_WRMSR
; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
xor eax, eax
xor edx, edx
mov ecx, AMD_AP_MTRR_FIX4k_C0000
CDLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_D8000
jbe CDLoop
; Set FFFFFh-E0000h as Uncacheable Memory
mov eax, 18181818h
mov edx, eax
mov ecx, AMD_AP_MTRR_FIX4k_E0000
EFLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_F8000
jbe EFLoop
; If IBV provided settings for Fixed-Sized MTRRs,
; overwrite the default settings.
.if ((esi != 0) && (esi != 0FFFFFFFFh))
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
; While we are not at the end of the list
.while (ecx != CPU_LIST_TERMINAL)
; Ensure that the MSR address is valid for Fixed-Sized MTRRs
.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
_WRMSR
.endif
add esi, sizeof (AP_MTRR_SETTINGS)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
.endw
.endif
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
.while (cl < 010h)
_WRMSR
inc cl
.endw
; Enable fixed-range and variable-range MTRRs
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Enable Top-of-Memory setting
; Enable use of RdMem/WrMem bits attributes
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MTRR_VAR_DRAM_EN ; Enable
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
bts eax, MTRR_FIX_DRAM_EN ; Enable
_WRMSR
mov esi, (1 SHL FLAG_IS_PRIMARY)
.else ; end if primary core
xor esi, esi
.endif
; Make sure not to touch any Shared MSR from this point on
AMD_DISABLE_STACK_FAMILY_HOOK
xor eax, eax
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ret
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteHltInstruction
ExecuteHltInstruction PROC NEAR C
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC NmiHandler
NmiHandler PROC NEAR C
iretd
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC GetCsSelector
GetCsSelector PROC NEAR C, CsSelector:PTR
push ax
push ebx
call FarCallGetCs
mov ebx, CsSelector
mov [ebx], ax
pop ebx
pop ax
ret
GetCsSelector ENDP
;======================================================================
; FarCallGetCs:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
; WARNING: This routine has a mirror routine in the PREMEM segment.
; These two routines MUST be sync'd for content.
;======================================================================
FarCallGetCs PROC FAR PRIVATE
mov ax, ss:[esp + 4]
retf
FarCallGetCs ENDP
;======================================================================
; SetIdtr:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
; WARNING: This routine has a mirror routine in the PREMEM segment.
; These two routines MUST be sync'd for content.
;======================================================================
PUBLIC SetIdtr
SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
lidt fword ptr ss:[ebx]
ret
SetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC ExecuteWbinvdInstruction
ExecuteWbinvdInstruction PROC NEAR C
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

157
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm
View File

@ -1,157 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
; */
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
text SEGMENT
;======================================================================
; ExecuteFinalHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteFinalHltInstruction PROC PUBLIC
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteHltInstruction PROC PUBLIC
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
NmiHandler PROC PUBLIC
iretq
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
GetCsSelector PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetCsSelector ENDP
;======================================================================
; SetIdtr:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
; WARNING: This routine has a mirror routine in the PREMEM segment.
; These two routines MUST be sync'd for content.
;======================================================================
SetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
SetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
ExecuteWbinvdInstruction PROC PUBLIC
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

497
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm
View File

@ -1,497 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 274#$ $Date: 2010-03-04 06:16:56 +0800 (Thu, 04 Mar 2010) $
; Description: Main memory controller system configuration for AGESA
;
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;memUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written
;
; Out:
;
; All registers preserved.
;===============================================================================
MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemUOutPort ENDP
;----------------------------------------------------------------------------
; _SFENCE();
;
_SFENCE macro
db 0Fh,0AEh,0F8h
endm
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemUWriteCachelines:
; Write a test pattern to DRAM
;
; In: Pattern - pointer to the write pattern
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
xor ecx, ecx
mov cx,ClCount
shl ecx,2
@@:
db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemUWriteCachelines ENDP
;===============================================================================
;MemUReadCachelines:
;
; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
;pattern is a stress pattern which exercises both ISI and crosstalk. The number
;of cache lines to fill is dependent on DCT width mode and burstlength.
;
; In: Buffer - pointer to a buffer where read data will be stored
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL Count:BYTE
pushad
; First, issue continuous dummy reads to fill up the cache
mov eax,Address
.if (ClCount > 18)
mov cx,ClCount
shr cx,4
mov Count,cl
.while (Count != 0)
push eax
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
pop eax
add eax,(16*64) ;Next 16CL
dec Count
.endw
.else
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
.if(ClCount == 1)
_MFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
.elseif(ClCount == 3)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
.elseif(ClCount == 6)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
.elseif(ClCount == 9)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
.elseif(ClCount == 18)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
mov eax,fs:[edx] ;TestAddr+16 cache lines
_MFENCE
mov eax,fs:[edx+64] ;TestAddr+17 cache lines
_MFENCE
.endif
.endif
_MFENCE
; Then, copy data to buffer
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
xor ecx, ecx
mov cx,ClCount
shl ecx,6
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemUReadCachelines ENDP
;===============================================================================
;MemUDummyCLRead:
;
; Perform a single cache line read from a given physical address.
;
; In: Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
_SFENCE
pushad
mov eax,Address
mov dl,fs:[eax]
popad
ret
MemUDummyCLRead ENDP
;===============================================================================
;MemUFlushPattern:
;
; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
;to ensure cache miss on the next read training.
;
; In: Address - Physical address to be flushed
; ClCount - number of cachelines to be flushed
; Out:
;
;All registers preserved.
;===============================================================================
MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
pushad
mov edi,Address
movzx ecx,ClCount
@@:
_MFENCE ; Force strong ordering of clflush
db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
_MFENCE
add edi,64
loop @B
popad
ret
MemUFlushPattern ENDP
;===============================================================================
;MemUGetWrLvNblErr:
; Read ClCount number of cachelines then return the bitmap that indicates
; the write leveling result of each byte lane.
;
; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
; Address - Physical address to be sampled
; ClCount - number of cachelines to be read
;
; OUT: ErrBitmap - WL result
;
;All registers preserved
;===============================================================================
MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL ZeroCount[32]:WORD
pushad
mov esi,Address
_EXECFENCE
;Cache fill
movzx ecx,ClCount
@@:
mov eax,fs:[esi]
add esi,64
loop @B
_MFENCE
; Then, count the number of 0's
;push es
;push ss
;pop es
lea edi,ZeroCount
mov cx,SIZEOF ZeroCount
mov al,0
rep stosb
;pop es
mov esi,Address
lea edi,ZeroCount
mov cx,ClCount
shl cx,6
.while(cx > 0)
mov al,fs:[esi]
test al,00Fh ;check lower nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
test al,0F0h ;check upper nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
inc esi
dec cx
test cx,07h
.if(ZERO?)
sub edi,(16*2)
sub cx,8
add esi,8
.endif
.endw
; Then, average and compress data to error bits
lea esi,ZeroCount
mov dx,ClCount
shl dx,1
xor eax,eax
xor ecx,ecx
mov cl,0
.while(cl<16)
.if(WORD PTR [esi] < dx)
bts eax,ecx
.endif
add esi,2
inc cl
.endw
xor edx,edx
mov dx,WORD PTR ErrBitmap
mov [edx], ax
popad
ret
MemUGetWrLvNblErr ENDP
;===============================================================================
;AlignPointerTo16Byte:
; Modifies BufferPtr to be 16 byte aligned
;
; In: BufferPtrPtr - Pointer to buffer pointer
; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
;
;All registers preserved.
;===============================================================================
AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
push edx
push eax
mov edx, BufferPtrPtr
mov eax, [edx]
add eax, 16
and ax, 0FFF0h
mov [edx], eax
pop eax
pop edx
ret
AlignPointerTo16Byte ENDP
;===============================================================================
;MemUMFenceInstr:
; Serialize instruction
;
; In:
; Out:
;
;All registers preserved.
;===============================================================================
MemUMFenceInstr PROC CALLCONV PUBLIC
_MFENCE
ret
MemUMFenceInstr ENDP
END

187
src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/mru.asm
View File

@ -1,187 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 237#$ $Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
; Description: Main memory controller system configuration for AGESA DDR 2
;
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;MemRecUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written to port
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemRecUOutPort ENDP
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemRecUWrite1CL:
;
; Write data from buffer to a system address
;
; In: Address - System address to read from
; Pattern - pointer pattern.
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
mov ecx,4
@@:
db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemRecUWrite1CL ENDP
;===============================================================================
;MemRecURead1CL:
;
; Read one cacheline to buffer
;
; In: Buffer - pointer buffer.
; : Address - System address to read from
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
pushad
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
mov ecx,64
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemRecURead1CL ENDP
;===============================================================================
;MemRecUFlushPattern:
;
; Flush one cache line
;
; In: Address - System address [31:0]
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
pushad
mov eax,Address
_EXECFENCE
;clflush fs:[eax]
db 064h ;access relative to FS BASE prefix
db 00Fh ;opcode
db 0AEh ;opcode
db 038h ;eax indirect addressing
_MFENCE
popad
ret
MemRecUFlushPattern ENDP
END

447
src/vendorcode/amd/agesa/f14/cpcarmac.inc
View File

@ -1,447 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Workfile: cpcarmac.inc $Revision:: 38483 $ $Date:: 2010-09-25 02:13:03 +0800 (Sat, 25 Sep 2010) $
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
.mmx
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; EBX = Return address (preserved)
;
; Out:
; SS:ESP - Our new private stack location
;
; EAX = AGESA_STATUS
;
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processor cores
; Preserved:
; ebx ebp
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es, ss, esp
; mmx0, mmx1
;
; Description:
; Fixed MTRR address allocation to cores:
; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
; There is a max of 1 BSP, 7 core0s and 56 other cores.
; Although each core has it's own cache storage, they share the address space. Each core must
; be assigned a private and unique address space for its stack. To support legacy systems,
; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
;
; 80000h 40000h 00000h
; +----------+----------+----------+----------+----------+----------+----------+----------+
; 64K | | | | | | | | | 64K ea
; ea +----------+----------+----------+----------+----------+----------+----------+----------+
; | MTRR 0000_0250 MTRRfix64K_00000 |
; +----------+----------+----------+----------+----------+----------+----------+----------+
; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
; +----------+----------+----------+----------+----------+----------+----------+----------+
;
; C0000h B0000h A0000h 90000h 80000h
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;16K | | | | | | | | | | | | | | | | |
; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;
; E0000h D0000h C0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;
; 100000h F0000h E0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;======================================================================
AMD_ENABLE_STACK MACRO
local AmdEnableStackExit
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
movd mm0, ebx ; Put return address in a safe place
movd mm1, ebp ; Save some other user registers
; get node id and core id of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
; If we detected an unknown processor family, return AGESA_FATAL.
.if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.endif
; determine if stack is already enabled. We are using the DefType MSR for this determination.
; It is =0 after reset; CAR setup sets it to enable the MTRRs
mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
.if (!(eax & CR0_MASK))
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
.if (eax & MSR_MASK)
bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
.endif
.endif
; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
mov ebx, esi ; Get my Node/Core info
xor bl, bl
shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
add ah, bh
mov ebx, eax ; Save PCI address for Base/Limit pair
mov dx, 0CF8h
out dx, eax
add dx, 4
xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
out dx, eax ; DRAM Limit = node0, no interleave
mov eax, ebx
sub eax, 4 ; Now point to the Base register
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 00000003h ; Set the read and write enable bits
out dx, eax ; DRAM Base = 0x0000, R/W
AMD_ENABLE_STACK_FAMILY_HOOK
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
_WRMSR
mov eax, esi
bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
.if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
.if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
; Clear all variable and Fixed MTRRs for non-shared cores
mov ecx, AMD_MTRR_VARIABLE_BASE0
xor eax, eax
xor edx, edx
.while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
_WRMSR
inc cl
.endw
mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
_WRMSR
mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
_WRMSR
mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
_WRMSR
mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
; - not strictly needed since the FixedMTRRs take presedence.
mov eax, (16 * 1024 * 1024)
mov ecx, TOP_MEM ; MSR:C001_001A
_WRMSR
.endif ; End Is_Primary
.endif ; End Stack_ReEntry
; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor eax, eax
xor edx, edx
mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
.while (cl != 1Ah)
_WRMSR
inc cl
.endw
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
; To prevent speculative reads from causing an eviction, the unused cache ranges are set
; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
; Note: some core stack regions will share an MTRR since the control granularity is much
; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
; space covered by the MTRR when parseling out cache space for the various uses. In some cases
; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
;
; Outcome of this block is that: (Note the MTRR map at the top of the file)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
;
mov ax, si ; Load node, core
.if (al == 0) ; Is a core 0?
.if (ah == 0) ; Is Node 0? (BSP)
; Is BSP, assign a 64K stack
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE / 1000h))
mov ebp, BSP_STACK_BASE_ADDR
.else ; node 1 to 7, core0
; Is a Core0 of secondary node, assign 16K stacks
mov bx, AMD_MTRR_FIX16k_80000
shl ebx, 16 ;
mov bh, ah ; Node# is used as slot#
mov bl, (CORE0_STACK_SIZE / 1000h)
mov al, ah ; Base = (Node# * Size);
mul bl ;
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE0_STACK_BASE_ADDR
mov ebp, eax
.endif
.else ;core 1 thru core 7
; Is core 1-7 of any node, assign 4K stacks
mov al, 8 ; CoreIndex = ( (Node# * 8) ...
mul ah ;
mov bx, si ;
add al, bl ; ... + Core#);
mov bx, AMD_MTRR_FIX64k_00000
shl ebx, 16 ;
mov bh, al ; Slot# = (CoreIndex / 16) + 4;
shr bh, 4 ;
add bh, 4 ;
mov bl, (CORE1_STACK_SIZE / 1000h)
mul bl ; Base = ( (CoreIndex * Size) ...
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
mov ebp, eax
.endif
; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
mov cl, bh ; ShiftCount = ((slot# ...
and cl, 03h ; ... % 4) ...
shl cl, 3 ; ... * 8);
shl edi, cl ; Cache type is now in correct position
ror ebx, 16 ; Get the MTRR address
movzx ecx, bx ;
rol ebx, 16 ; Put slot# & size back in BX
_RDMSR ; Read-modify-write the MSR
.if (bh < 4) ; Is value in lower or upper half of MSR?
or eax, edi ;
.else ;
or edx, edi ;
.endif ;
_WRMSR ;
; Enable MTRR defaults as UC type
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Read-modify-write the MSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Close the modification window on the Fixed MTRRs
mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, CR0_PG ; Make sure paging is disabled
btr eax, CR0_CD ; Clear CR0 NW and CD
btr eax, CR0_NW
mov CR0, eax
; Use the Stack Base & size to calculate SS and ESP values
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
;
mov esp, ebp ; Initialize the stack pointer
mov edi, esp ; Copy the stack start to edi
movzx bx, bl
movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
shl ebx, 12 ; Make size full byte count (* 4K)
add esp, ebx ; Set the Stack Pointer as full linear address
sub esp, 4
;
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - 32b start address of stack block
; ebx - size of stack block
; esp - 32b linear stack pointer
;
; Determine mode for SS base;
mov ecx, CR0 ; Check for 32-bit protect mode
bt ecx, CR0_PE ;
.if (!carry?) ; PE=0 means real mode
mov cx, cs ;
.if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
; alter SS:ESP for 16b Real Mode:
mov eax, edi ;
shr eax, 4 ; Create a Real Mode segment for ss, ds, es
mov ss, ax ;
mov ds, ax ;
mov es, ax ;
shl eax, 4 ;
sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
mov esp, ebx ; Make SP an offset from SS
sub esp, 4 ;
.endif ; endif
; else
; Default is to use Protected 32b Mode
.endif
;
; Clear The Stack
; Now that we have set the location and the MTRRs, initialize the cache by
; reading then writing to zero all of the stack area.
; review:
; ss - Stack base
; esp - stack pointer
; ebx - size of stack block
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - address of start of stack block
;
shr ebx, 2 ;
mov cx, bx ; set cx for size count of DWORDS
; Check our flags - Don't clear an existing stack
.if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
cld
mov esi, edi
rep lods DWORD PTR [esi] ; Pre-load the range
xor eax, eax
mov cx, bx
mov esi, edi ; Preserve base for push on stack
rep stos DWORD PTR [edi] ; Clear the range
mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
shl ebx, 2 ; Put stack size and base
push ebx ; in top of stack
push esi
mov ecx, ebx ; Return size of stack in bytes
mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
.else
movzx ecx, cx
shl ecx, 2 ; Return size of stack, in bytes
mov eax, esi
shr eax, 24 ; Keep the flags as part of the error report
or eax, 40000000h ; eax = AGESA_WARNING (Stack has already been set up)
.endif
AmdEnableStackExit:
movd ebx, mm0 ; Restore return address
movd ebp, mm1
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_SUCCESS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; Save return address
; get node/core/flags of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
_WRMSR
; Set lower 640K MTRRs for Write-Back memory caching
mov ecx, AMD_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR ; 0 - 512K = WB Mem
mov ecx, AMD_MTRR_FIX16k_80000
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
mov ebx, esp ; restore return address (ebx)
xor eax, eax
ENDM

670
src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc
View File

@ -1,670 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
;
; ****************************************************************************
; *
; * Copyright (C) 2012 Advanced Micro Devices, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; * * Redistributions of source code must retain the above copyright
; * notice, this list of conditions and the following disclaimer.
; * * Redistributions in binary form must reproduce the above copyright
; * notice, this list of conditions and the following disclaimer in the
; * documentation and/or other materials provided with the distribution.
; * * Neither the name of Advanced Micro Devices, Inc. nor the names of
; * its contributors may be used to endorse or promote products derived
; * from this software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
LR_DIMM0 EQU 0001h
LR_DIMM1 EQU 0010h
LR_DIMM2 EQU 0100h
LR_DIMM3 EQU 1000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
; <
; < CS POPULATION MASKS
;
CS_ANY_ EQU 0FFh
CS0_ EQU 01h
CS1_ EQU 02h
CS2_ EQU 04h
CS3_ EQU 08h
CS4_ EQU 10h
CS5_ EQU 20h
CS6_ EQU 40h
CS7_ EQU 80h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
;
; DIMM VOLTAGE MASK
;
VOLT_ANY_ EQU 0FFh
VOLT1_5_ EQU 01h
VOLT1_35_ EQU 02h
VOLT1_25_ EQU 04h
;
; NOT APPLICIABLE
;
NA_ EQU 00h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; **********************************
; * TABLE DRIVEN PSO SPECIFIC ENTRIES
; **********************************
; Condition descriptor
PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
; Overriding entry types
PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
PSO_TBLDRV____TRAINING EQU 222 ; < training
PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
DB PSO_CPU_FAMILY_TO_OVERRIDE
DB 4
DD CpuFamilyRevision
ENDM
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 7
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 4
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 7
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 12
DB SocketID
DB ChannelID
DB DimmID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 21
DB SocketID
DB ChannelID
DB DimmID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 4
DB ANY_SOCKET
DB ANY_CHANNEL
DB ALL_DIMMS
DB 1
ENDM
MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
DB PSO_MIN_RD_WR_DATAEYE_WIDTH
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB MinRdDataeyeWidth
DB MinWrDataeyeWidth
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
; *****************************************************************************************
; *
; * TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************
; Configuration sub-descriptors
CONFIG_GENERAL EQU 0
CONFIG_SPEEDLIMIT EQU 1
CONFIG_RC2IBT EQU 2
CONFIG_DONT_CARE EQU 3
Config_Type TEXTEQU <DWORD>
;
; Configuration Macros
;
TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
DB PSO_TBLDRV_CONFIG
DB 9
DB CONFIG_GENERAL
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
ENDM
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
DB PSO_TBLDRV_CONFIG
DB 7
DB CONFIG_SPEEDLIMIT
DB DimmPerCH
DB Dimms
DB NumOfSR
DB NumOfDR
DB NumOfQR
DB NumOfLRDimm
ENDM
TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
DB PSO_TBLDRV_CONFIG
DB 10
DB CONFIG_RC2IBT
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
DB NumOfReg
ENDM
;
; Overriding Macros
;
TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
DB PSO_TBLDRV_SPEEDLIMIT
DB 6
DW SpeedLimit1_5
DW SpeedLimit1_35
DW SpeedLimit1_25
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
DB PSO_TBLDRV_ODT_RTTNOM
DB 2
DB TgtCS
DB RttNom
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
DB PSO_TBLDRV_ODT_RTTWR
DB 2
DB TgtCS
DB RttWr
ENDM
TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
DB PSO_TBLDRV_ODTPATTERN
DB 16
DD RdODTCSHigh
DD RdODTCSLow
DD WrODTCSHigh
DD WrODTCSLow
ENDM
TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
DB PSO_TBLDRV_ADDRTMG
DB 4
DD AddrTmg
ENDM
TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
DB PSO_TBLDRV_ODCCTRL
DB 4
DD OdcCtrl
ENDM
TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
DB PSO_TBLDRV_SLOWACCMODE
DB 1
DB SlowAccMode
ENDM
TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
DB PSO_TBLDRV_RC2_IBT
DB 2
DB TgtDimm
DB IBT
ENDM
TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_CL
DB 3
DB RegValOfTcl
DB MR0CL13
DB MR0CL0
ENDM
TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_WR
DB 2
DB RegValOfTcl
DB MR0WR
ENDM
TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_RC10_OPSPEED
DB 5
DD Frequency
DB MR10OPSPEED
ENDM
TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
DB PSO_TBLDRV_LRDIMM_IBT
DB 4
DB F0RC8
DB F1RC0
DB F1RC1
DB F1RC2
ENDM
TBLDRV_CONFIG_ENTRY____TRAINING MACRO Training__Mode:REQ
DB PSO_TBLDRV____TRAINING
DB 1
DB Training__Mode
ENDM
;
; Macros for removing entries
;
INVALID_CONFIG_FLAG EQU 8000h
TBLDRV_INVALID_CONFIG MACRO
DB PSO_TBLDRV_INVALID_TYPE
DB 0
ENDM
; *****************************************************************************************
; *
; * END OF TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************

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; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
;
; ****************************************************************************
; *
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

575
src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc
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@ -1,575 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
;
; ****************************************************************************
;
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

671
src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm
View File

@ -1,671 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.xmm
.model flat
ASSUME FS:NOTHING
.code
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo8
WriteIo8 PROC NEAR C USES DX AX Address:WORD, Data:Byte
mov dx, Address
mov al, Data
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo16
WriteIo16 PROC NEAR C USES DX AX Address:WORD, Data:WORD
mov dx, Address
mov ax, Data
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] Address IO port address
; * @param[in] Data IO port Value
; */
public WriteIo32
WriteIo32 PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
mov dx, Address
mov eax, Data
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] - IO port address
; * @retval IO port Value
; */
public ReadIo8
ReadIo8 PROC NEAR C USES DX Address:WORD
mov dx, Address
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] Address IO port address
; * @retval IO port Value
; */
public ReadIo16
ReadIo16 PROC NEAR C USES DX Address:WORD
mov dx, Address
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] Address IO port address
; * @retval IO port Value
; */
public ReadIo32
ReadIo32 PROC NEAR C USES DX Address:WORD
mov dx, Address
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] Address MSR Address
; * @param[in] Data Pointer to data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdMsrRead
LibAmdMsrRead PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov ecx, Address
rdmsr
mov esi, Value
mov [esi], eax
mov [esi+4], edx
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] Address MSR Address
; * @param[in] Data Pointer to data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdMsrWrite
LibAmdMsrWrite PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov ecx, Address
mov esi, Data
mov eax, [esi]
mov edx, [esi+4]
wrmsr
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] Func CPUID function
; * @param[in] DATA Pointer to CPUID_DATA to save cpuid data
; * @param[in] ConfigPtr (Optional)
; */
public LibAmdCpuidRead
LibAmdCpuidRead PROC NEAR C Func:DWORD, DATA:PTR, ConfigPtr:PTR
pushad
mov esi, ConfigPtr ;Dummy read to avoid compilation warning
mov eax, Func
cpuid
mov esi, DATA
mov [esi], eax
mov [esi+4], ebx
mov [esi+8], ecx
mov [esi+12],edx
popad
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; *
; */
public ReadTSC
ReadTSC PROC NEAR C
rdtsc
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Set FS_BASE
; *
; *
; *
; * @param[in] esi - Low Dword of physical address
; * @param[in] edi - High Dword of physical address
; */
SetFsBase PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
mov eax, ecx
mov ecx, 0C0010015h ; HWCR
rdmsr
mov ebx, eax
bts eax, 17 ; HWCR.Wrap32Dis
wrmsr
xchg edx, edi
mov eax, esi
mov esi, ebx
mov ecx, 0C0000100h ; FS_BASE
wrmsr
ret
SetFsBase ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Restore MSR0C001_0015
; *
; * @param[in] esi - Low Dword
; * @param[in] edi - High Dword
; */
RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
mov ecx, 0C0010015h
mov eax, esi
mov edx, edi
wrmsr
ret
RestoreHwcr ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] Address - Memory Address
; * @retval Memory byte at given address
; */
Read64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov al, fs:[ebx]
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov al, ds:[esi]
Done:
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] Address - Memory Address
; * @retval Memory word at given address
; */
Read64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov ax, fs:[ebx]
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov ax, ds:[esi]
Done:
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] Address - Memory Address
; * @retval Memory dword at given address
; */
Read64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov eax, fs:[ebx]
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov eax, ds:[esi]
Done:
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem8 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:BYTE
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov al, Data
mov fs:[ebx], al
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov al, Data
mov ds:[esi], al
Done:
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem16 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:WORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov ax, Data
mov fs:[ebx], ax
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov ax, Data
mov ds:[esi], ax
Done:
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] Address - Memory Address
; * @param[in] Value - Value to write
; */
Write64Mem32 PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:DWORD
mov esi, DWORD PTR Address[0]
mov edi, DWORD PTR Address[4]
test edi, edi
jz AccesBelow4G
push fs
call SetFsBase
xor ebx, ebx
mov eax, Data
mov fs:[ebx], eax
call RestoreHwcr
pop fs
jmp Done
AccesBelow4G:
mov eax, Data
mov ds:[esi], eax
Done:
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] Value Value to write
; */
LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
pushad
push ds
.if(Reg == 00h)
mov eax, cr0
.elseif(Reg == 04h)
mov eax, cr4
.elseif(Reg == 10h)
mov eax, dr0
.elseif(Reg == 11h)
mov eax, dr1
.elseif(Reg == 12h)
mov eax, dr2
.elseif(Reg == 13h)
mov eax, dr3
.elseif(Reg == 17h)
mov eax, dr7
.else
xor eax,eax
.endif
mov edi, Value
mov [edi], eax
pop ds
popad
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] Reg Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] Value Value to write
; */
LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
mov eax, Value
.if(Reg == 00h)
mov cr0, eax
.elseif(Reg == 4)
mov cr4, eax
.elseif(Reg == 10h)
mov dr0, eax
.elseif(Reg == 11h)
mov dr1, eax
.elseif(Reg == 12h)
mov dr2, eax
.elseif(Reg == 13h)
mov dr3, eax
.elseif(Reg == 17h)
mov dr7, eax
.endif
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC NEAR C
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC NEAR C
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC NEAR C
pushad
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popad
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] Address IO Port Address
; * @param[in] Value Value to write
; * @param[in] Flag IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
push edx
push eax
push ebx
mov edx, Address
mov eax, Value
mov ebx, Flag
out dx, eax
pop ebx
pop eax
pop edx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC NEAR C
pushad
mov ecx, 0C001100Ah ;bit 0 = HDT redirect
mov edi, 09C5A203Ah ;Password
RDMSR ;
or al, 1 ;
WRMSR ;
mov al, 0B2h ;Marker = B2
db 0F1h ;ICEBP
popad
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with .
; *
; * @param[in] Value Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC NEAR C Value:DWORD
mov eax, Value
bsf eax, Value
.if (Zero?)
mov al,32
.endif
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] Value Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC NEAR C Value:DWORD
mov eax, Value
bsr eax, Value
.if (Zero?)
mov al,0FFh
.endif
ret
LibAmdBitScanReverse ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Flush specified number of cache line
; *
; * @param[in] Address Physical address to be flushed
; * @param[in] Count number of cachelines to be flushed
; */
PUBLIC LibAmdCLFlush
LibAmdCLFlush PROC NEAR C Address:QWORD, Count:BYTE
pushad
mov ecx, 0C0010015h ; HWCR
rdmsr
mov esi, eax
mov edi, edx
bts eax, 17 ; HWCR.Wrap32Dis
wrmsr
xor eax, eax
mov edx, DWORD PTR Address[4]
mov ecx, 0C0000100h ; FS_BASE
wrmsr
mov eax, DWORD PTR Address[0]
movzx ecx, Count
@@:
mfence
clflush fs:[eax]
mfence
add eax,64
loop @B
call RestoreHwcr
popad
ret
LibAmdCLFlush ENDP
END

110
src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm
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@ -1,110 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the right.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_aullshr PROC NEAR C PUBLIC
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov eax, edx
xor edx, edx
.endif
shrd eax, edx, cl
shr edx, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_aullshr ENDP
;/*++
;
;Routine Description:
;
; Shifts a UINT64 to the left.
;
;Arguments:
;
; EDX:EAX - UINT64 value to be shifted
; CL - Shift count
;
;Returns:
;
; EDX:EAX - shifted value
;
;--*/
_allshl PROC NEAR C PUBLIC USES CX
.if (cl < 64)
.if (cl >= 32)
sub cl, 32
mov edx, eax
xor eax, eax
.endif
shld edx, eax, cl
shl eax, cl
.else
xor eax, eax
xor edx, edx
.endif
ret
_allshl ENDP
END

84
src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm
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@ -1,84 +0,0 @@
;/**
; * @file
; *
; * Agesa library 32bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
; void *memcpy( void *dest, void *src, size_t count );
;
; Copy count bytes from src to dest, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memcpy
memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov esi, src
mov ecx, count
rep movsb
mov eax, dest
popf
ret
memcpy ENDP
; void *memset( void *dest, int c, size_t count );
;
; At dest, set count bytes to byte value, returning dest.
; ("c" is not legal as an assembly parameter name, replaced with value.)
; Assume ES is set appropriately, 32 bit flat.
;
public memset
memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
pushf
cld ; We will increment through *dest
mov edi, dest
mov eax, value
mov ecx, count
rep stosb
mov eax, edi
popf
ret
memset ENDP
END

591
src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm
View File

@ -1,591 +0,0 @@
;/**
; * @file
; *
; * Agesa library 64bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.code
;/*++
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] CX IO port address
; * @param[in] DL IO port Value
; */
PUBLIC WriteIo8
WriteIo8 PROC
mov al, dl
mov dx, cx
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] CX IO port address
; * @param[in] DX IO port Value
; */
PUBLIC WriteIo16
WriteIo16 PROC
mov ax, dx
mov dx, cx
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] CX IO port address
; * @param[in] EDX IO port Value
; */
PUBLIC WriteIo32
WriteIo32 PROC
mov eax, edx
mov dx, cx
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] CX IO port address
; * @retval AL IO port Value
; */
PUBLIC ReadIo8
ReadIo8 PROC
mov dx, cx
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] CX IO port address
; * @retval AX IO port Value
; */
PUBLIC ReadIo16
ReadIo16 PROC
mov dx, cx
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] CX IO port address
; * @retval EAX IO port Value
; */
PUBLIC ReadIo32
ReadIo32 PROC
mov dx, cx
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrRead
LibAmdMsrRead PROC
push rsi
mov rsi, rdx
rdmsr
mov [rsi], eax
mov [rsi+4], edx
pop rsi
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrWrite
LibAmdMsrWrite PROC
push rsi
mov rsi, rdx
mov eax, [rsi]
and rax, 0ffffffffh
mov edx, [rsi+4]
and rdx, 0ffffffffh
wrmsr
pop rsi
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] RCX CPUID function
; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdCpuidRead
LibAmdCpuidRead PROC
push rbx
push rsi
mov rsi, rdx
mov rax, rcx
cpuid
mov [rsi], eax
mov [rsi+4], ebx
mov [rsi+8], ecx
mov [rsi+12],edx
pop rsi
pop rbx
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; * @retval RAX Time stamp counter value
; */
PUBLIC ReadTSC
ReadTSC PROC
rdtsc
and rax, 0ffffffffh
shl rdx, 32
or rax, rdx
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] RCX - Memory Address
; * @retval Memory byte at given address
; */
PUBLIC Read64Mem8
Read64Mem8 PROC
xor rax, rax
mov al, [rcx]
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] RCX - Memory Address
; * @retval Memory word at given address
; */
PUBLIC Read64Mem16
Read64Mem16 PROC
xor rax, rax
mov ax, [rcx]
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] RCX - Memory Address
; * @retval Memory dword at given address
; */
PUBLIC Read64Mem32
Read64Mem32 PROC
xor rax, rax
mov eax, [rcx]
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] RCX Memory Address
; * @param[in] DL Value to write
; */
PUBLIC Write64Mem8
Write64Mem8 PROC
xor rax, rax
mov rax, rdx
mov [rcx], al
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] RCX Memory Address
; * @param[in] DX Value to write
; */
PUBLIC Write64Mem16
Write64Mem16 PROC
xor rax, rax
mov rax, rdx
mov [rcx], ax
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] RCX Memory Address
; * @param[in] EDX Value to write
; */
PUBLIC Write64Mem32
Write64Mem32 PROC
xor rax, rax
mov rax, rdx
mov [rcx], eax
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Pointer to value
; */
PUBLIC LibAmdReadCpuReg
LibAmdReadCpuReg PROC
push rax
xor rax, rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
jmp RegRead
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
jmp RegRead
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
jmp RegRead
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
jmp RegRead
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
jmp RegRead
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
jmp RegRead
Reg17h:
cmp cl, 17h
jne RegRead
mov rax, dr7
RegRead:
mov [rdx], eax
pop rax
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Value to write
; */
PUBLIC LibAmdWriteCpuReg
LibAmdWriteCpuReg PROC
push rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
mov eax, edx
mov cr0, rax
jmp Done
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
mov eax, edx
mov cr4, rax
jmp Done
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
mov eax, edx
mov dr0, rax
jmp Done
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
mov eax, edx
mov dr1, rax
jmp Done
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
mov eax, edx
mov dr2, rax
jmp Done
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
mov eax, edx
mov dr3, rax
jmp Done
Reg17h:
cmp cl, 17h
jne Done
mov rax, dr7
mov eax, edx
mov dr7, rax
Done:
pop rax
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC
pushfq
mov rax, 0BACCD00Bh ; Backdoor in SimNow
mov rbx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popfq
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] ECX IO Port Address
; * @param[in] EDX Value to write
; * @param[in] R8D IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC
push rbx
push rax
mov ebx, r8d
mov eax, edx
mov edx, ecx
out dx, eax
pop rax
pop rbx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC
push rbx
mov rcx, 0C001100Ah ;bit 0 = HDT redirect
mov rdi, 09C5A203Ah ;Password
rdmsr
and rax, 0ffffffffh
or rax, 1
wrmsr
mov rax, 0B2h ;Marker = B2
db 0F1h ;ICEBP
pop rbx
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC
bsf eax, ecx
jnz nonZeroSource
mov al,32
nonZeroSource:
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC
bsr eax, ecx
jnz nonZeroSource
mov al,0FFh
nonZeroSource:
ret
LibAmdBitScanReverse ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Flush specified number of cache line
; *
; * @param[in] RCX Physical address to be flushed
; * @param[in] DL number of cachelines to be flushed
; */
PUBLIC LibAmdCLFlush
LibAmdCLFlush PROC
push rax
mov rax, rcx
movzx rcx, dl
@@:
mfence
clflush [rax]
mfence
add rax,64
loop @B
pop rax
ret
LibAmdCLFlush ENDP
END

113
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
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@ -1,113 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; LocalPciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, LocalPciRegister:DWORD
mov ecx, 0C001001Fh
rdmsr
push eax
push ecx
push edx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, LocalPciRegister
mov edx, PciAddress
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dx, 0CF8h ; Set Reg Config Space
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax
db 0Fh, 0AEh, 0F0h ; MFENCE
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
db 0Fh, 0AEh, 0F0h ; MFENCE
out dx, eax ; move data to return position
db 0Fh, 0AEh, 0F0h ; MFENCE
pop edx
pop ecx
pop eax
wrmsr
ret
F10RevDProbeFilterCritical ENDP
END

127
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
View File

@ -1,127 +0,0 @@
;/**
; * @file
; *
; * AGESA Family 10h Revision D support routines.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU/F10
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
.LIST
;===============================================
;===============================================
;==
;== M E M O R Y P R E S E N T S E G M E N T
;==
;===============================================
;===============================================
.CODE
;======================================================================
; F10RevDProbeFilterCritical: Performs critical sequence for probe
; filter initialization.
;
; In:
; PciAddress Full PCI address of the node to init
; LocalPciRegister Current value of F3x1D4
;
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC F10RevDProbeFilterCritical
F10RevDProbeFilterCritical PROC
push rax
push rcx
push rdx
push rsi
push rdi
mov esi, ecx
mov edi, edx
mov ecx, 0C001001Fh
rdmsr
push rax
push rcx
push rdx
or dh, 40h
wrmsr
mov eax, 810003D4h
mov ecx, edi
mov edx, esi
shr edx, 4
and dh, 0F8h
or ah, dh
or cl, 2
mfence
mov dx, 0CF8h ; Set Reg Config Space
mfence
out dx, eax
mfence
mov dl, 0FCh ; Set DX to Pci Config Data
mov eax, ecx ;Set config Reg data
mfence
out dx, eax ; move data to return position
mfence
pop rdx
pop rcx
pop rax
wrmsr
pop rdi
pop rsi
pop rdx
pop rcx
pop rax
ret
F10RevDProbeFilterCritical ENDP
END

362
src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm
View File

@ -1,362 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 47763 $ @e \$Date: 2011-02-27 18:11:57 -0700 (Sun, 27 Feb 2011) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE agesa.inc
INCLUDE cpcarmac.inc
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y A B S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; ExecuteFinalHltInstruction: Disables the stack and performs
; a hlt instruction on an AP.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteFinalHltInstruction
ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
mov esi, HaltFlags
mov edi, ApMtrrSettingList
; Do these special steps in case if the core is part of a compute unit
; Note: The following bits are family specific flags, that gets set during build time,
; and indicates things like "family cache control methodology", etc.
; esi bit0 = 0 -> not a Primary core
; esi bit0 = 1 -> Primary core
; esi bit1 = 0 -> Cache disable
; esi bit1 = 1 -> Cache enable
.if (esi & 2h)
; Set CombineCr0Cd bit
mov ecx, CU_CFG3
_RDMSR
bts edx, (COMBINE_CR0_CD - 32)
_WRMSR
; Clear the CR0.CD bit
mov eax, CR0 ; Make sure cache is enabled for all APs
btr eax, CR0_CD
btr eax, CR0_NW
mov CR0, eax ; Write back to CR0
.else
mov eax, CR0 ; Make sure cache is disabled for all APs
bts eax, CR0_CD ; Disable cache
bts eax, CR0_NW
mov CR0, eax ; Write back to CR0
.endif
.if (esi & 1h)
; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
mov esi, edi ; Get ApMtrrSettingList
; Configure the MTRRs on the AP so
; when it runs remote code it will execute
; out of RAM instead of ROM.
; Disable MTRRs and turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MTRR_VAR_DRAM_EN ; Disable
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
btr eax, MTRR_FIX_DRAM_EN ; Disable
bts eax, SYS_UC_LOCK_EN
_WRMSR
; Setup default values for Fixed-Sized MTRRs
; Set 7FFFh-00000h as WB
mov ecx, AMD_AP_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR
; Set 9FFFFh-80000h also as WB
mov ecx, AMD_AP_MTRR_FIX16k_80000
_WRMSR
; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
mov ecx, AMD_AP_MTRR_FIX16k_A0000
xor eax, eax
xor edx, edx
_WRMSR
; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
xor eax, eax
xor edx, edx
mov ecx, AMD_AP_MTRR_FIX4k_C0000
CDLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_D8000
jbe CDLoop
; Set FFFFFh-E0000h as Uncacheable Memory
mov eax, 18181818h
mov edx, eax
mov ecx, AMD_AP_MTRR_FIX4k_E0000
EFLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_F8000
jbe EFLoop
; If IBV provided settings for Fixed-Sized MTRRs,
; overwrite the default settings.
.if ((esi != 0) && (esi != 0FFFFFFFFh))
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
; While we are not at the end of the list
.while (ecx != CPU_LIST_TERMINAL)
; Ensure that the MSR address is valid for Fixed-Sized MTRRs
.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
_WRMSR
.endif
add esi, sizeof (AP_MTRR_SETTINGS)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
.endw
.endif
; Enable fixed-range and variable-range MTRRs
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Enable Top-of-Memory setting
; Enable use of RdMem/WrMem bits attributes
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MTRR_VAR_DRAM_EN ; Enable
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
bts eax, MTRR_FIX_DRAM_EN ; Enable
_WRMSR
mov esi, (1 SHL FLAG_IS_PRIMARY)
.else ; end if primary core
xor esi, esi
.endif
; Make sure not to touch any Shared MSR from this point on
AMD_DISABLE_STACK_FAMILY_HOOK
bt esi, FLAG_IS_PRIMARY
.if (carry?)
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
.while (cx >= AMD_MTRR_VARIABLE_BASE6)
_WRMSR
dec cx
.endw
.endif
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ret
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteHltInstruction
ExecuteHltInstruction PROC NEAR C
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC NmiHandler
NmiHandler PROC NEAR C
iretd
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC GetCsSelector
GetCsSelector PROC NEAR C, CsSelector:PTR
push ax
push ebx
call FarCallGetCs
mov ebx, CsSelector
mov [ebx], ax
pop ebx
pop ax
ret
GetCsSelector ENDP
;======================================================================
; FarCallGetCs:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
FarCallGetCs PROC FAR PRIVATE
mov ax, ss:[esp + 4]
retf
FarCallGetCs ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC SetIdtr
SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
lidt fword ptr ss:[ebx]
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC GetIdtr
GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
sidt fword ptr ss:[ebx]
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC ExecuteWbinvdInstruction
ExecuteWbinvdInstruction PROC NEAR C
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

174
src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm
View File

@ -1,174 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
text SEGMENT
;======================================================================
; ExecuteFinalHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteFinalHltInstruction PROC PUBLIC
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteHltInstruction PROC PUBLIC
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
NmiHandler PROC PUBLIC
iretq
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
GetCsSelector PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetCsSelector ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
SetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
GetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
ExecuteWbinvdInstruction PROC PUBLIC
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

497
src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm
View File

@ -1,497 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
; Description: Main memory controller system configuration for AGESA
;
;
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;memUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written
;
; Out:
;
; All registers preserved.
;===============================================================================
MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemUOutPort ENDP
;----------------------------------------------------------------------------
; _SFENCE();
;
_SFENCE macro
db 0Fh,0AEh,0F8h
endm
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemUWriteCachelines:
; Write a test pattern to DRAM
;
; In: Pattern - pointer to the write pattern
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
xor ecx, ecx
mov cx,ClCount
shl ecx,2
@@:
db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemUWriteCachelines ENDP
;===============================================================================
;MemUReadCachelines:
;
; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
;pattern is a stress pattern which exercises both ISI and crosstalk. The number
;of cache lines to fill is dependent on DCT width mode and burstlength.
;
; In: Buffer - pointer to a buffer where read data will be stored
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL Count:BYTE
pushad
; First, issue continuous dummy reads to fill up the cache
mov eax,Address
.if (ClCount > 18)
mov cx,ClCount
shr cx,4
mov Count,cl
.while (Count != 0)
push eax
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
pop eax
add eax,(16*64) ;Next 16CL
dec Count
.endw
.else
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
.if(ClCount == 1)
_MFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
.elseif(ClCount == 3)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
.elseif(ClCount == 6)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
.elseif(ClCount == 9)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
.elseif(ClCount == 18)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
mov eax,fs:[edx] ;TestAddr+16 cache lines
_MFENCE
mov eax,fs:[edx+64] ;TestAddr+17 cache lines
_MFENCE
.endif
.endif
_MFENCE
; Then, copy data to buffer
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
xor ecx, ecx
mov cx,ClCount
shl ecx,6
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemUReadCachelines ENDP
;===============================================================================
;MemUDummyCLRead:
;
; Perform a single cache line read from a given physical address.
;
; In: Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
_SFENCE
pushad
mov eax,Address
mov dl,fs:[eax]
popad
ret
MemUDummyCLRead ENDP
;===============================================================================
;MemUFlushPattern:
;
; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
;to ensure cache miss on the next read training.
;
; In: Address - Physical address to be flushed
; ClCount - number of cachelines to be flushed
; Out:
;
;All registers preserved.
;===============================================================================
MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
pushad
mov edi,Address
movzx ecx,ClCount
@@:
_MFENCE ; Force strong ordering of clflush
db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
_MFENCE
add edi,64
loop @B
popad
ret
MemUFlushPattern ENDP
;===============================================================================
;MemUGetWrLvNblErr:
; Read ClCount number of cachelines then return the bitmap that indicates
; the write leveling result of each byte lane.
;
; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
; Address - Physical address to be sampled
; ClCount - number of cachelines to be read
;
; OUT: ErrBitmap - WL result
;
;All registers preserved
;===============================================================================
MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL ZeroCount[32]:WORD
pushad
mov esi,Address
_EXECFENCE
;Cache fill
movzx ecx,ClCount
@@:
mov eax,fs:[esi]
add esi,64
loop @B
_MFENCE
; Then, count the number of 0's
;push es
;push ss
;pop es
lea edi,ZeroCount
mov cx,SIZEOF ZeroCount
mov al,0
rep stosb
;pop es
mov esi,Address
lea edi,ZeroCount
mov cx,ClCount
shl cx,6
.while(cx > 0)
mov al,fs:[esi]
test al,00Fh ;check lower nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
test al,0F0h ;check upper nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
inc esi
dec cx
test cx,07h
.if(ZERO?)
sub edi,(16*2)
sub cx,8
add esi,8
.endif
.endw
; Then, average and compress data to error bits
lea esi,ZeroCount
mov dx,ClCount
shl dx,1
xor eax,eax
xor ecx,ecx
mov cl,0
.while(cl<16)
.if(WORD PTR [esi] < dx)
bts eax,ecx
.endif
add esi,2
inc cl
.endw
xor edx,edx
mov dx,WORD PTR ErrBitmap
mov [edx], ax
popad
ret
MemUGetWrLvNblErr ENDP
;===============================================================================
;AlignPointerTo16Byte:
; Modifies BufferPtr to be 16 byte aligned
;
; In: BufferPtrPtr - Pointer to buffer pointer
; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
;
;All registers preserved.
;===============================================================================
AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
push edx
push eax
mov edx, BufferPtrPtr
mov eax, [edx]
add eax, 16
and ax, 0FFF0h
mov [edx], eax
pop eax
pop edx
ret
AlignPointerTo16Byte ENDP
;===============================================================================
;MemUMFenceInstr:
; Serialize instruction
;
; In:
; Out:
;
;All registers preserved.
;===============================================================================
MemUMFenceInstr PROC CALLCONV PUBLIC
_MFENCE
ret
MemUMFenceInstr ENDP
END

187
src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/mru.asm
View File

@ -1,187 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 443#$ $Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
; Description: Main memory controller system configuration for AGESA DDR 2
;
;
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;MemRecUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written to port
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemRecUOutPort ENDP
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemRecUWrite1CL:
;
; Write data from buffer to a system address
;
; In: Address - System address to read from
; Pattern - pointer pattern.
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
mov ecx,4
@@:
db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemRecUWrite1CL ENDP
;===============================================================================
;MemRecURead1CL:
;
; Read one cacheline to buffer
;
; In: Buffer - pointer buffer.
; : Address - System address to read from
;
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
pushad
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
mov ecx,64
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemRecURead1CL ENDP
;===============================================================================
;MemRecUFlushPattern:
;
; Flush one cache line
;
; In: Address - System address [31:0]
; Out:
;
;All registers preserved except for "Out:"
;===============================================================================
MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
pushad
mov eax,Address
_EXECFENCE
;clflush fs:[eax]
db 064h ;access relative to FS BASE prefix
db 00Fh ;opcode
db 0AEh ;opcode
db 038h ;eax indirect addressing
_MFENCE
popad
ret
MemRecUFlushPattern ENDP
END

457
src/vendorcode/amd/agesa/f15/cpcarmac.inc
View File

@ -1,457 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Workfile: cpcarmac.inc $Revision:: 50472 $ $Date:: 2011-04-11 01:57:56 -0600 (Mon, 11 Apr 2011) $
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
.mmx
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; EBX = Return address (preserved)
;
; Out:
; SS:ESP - Our new private stack location
;
; EAX = AGESA_STATUS
; EDX = Return status code if EAX contains a return code of higher
; severity than AGESA_SUCCESS
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processor cores
; Preserved:
; ebx ebp
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es, ss, esp
; mmx0, mmx1, mmx5
;
; Description:
; Fixed MTRR address allocation to cores:
; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
; There is a max of 1 BSP, 7 core0s and 56 other cores.
; Although each core has it's own cache storage, they share the address space. Each core must
; be assigned a private and unique address space for its stack. To support legacy systems,
; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
;
; 80000h 40000h 00000h
; +----------+----------+----------+----------+----------+----------+----------+----------+
; 64K | | | | | | | | | 64K ea
; ea +----------+----------+----------+----------+----------+----------+----------+----------+
; | MTRR 0000_0250 MTRRfix64K_00000 |
; +----------+----------+----------+----------+----------+----------+----------+----------+
; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
; +----------+----------+----------+----------+----------+----------+----------+----------+
;
; C0000h B0000h A0000h 90000h 80000h
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;16K | | | | | | | | | | | | | | | | |
; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;
; E0000h D0000h C0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;
; 100000h F0000h E0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;======================================================================
AMD_ENABLE_STACK MACRO
local AmdEnableStackExit
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
movd mm0, ebx ; Put return address in a safe place
movd mm1, ebp ; Save some other user registers
; get node id and core id of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
; If we detected an unknown processor family or core combination, return AGESA_FATAL.
.if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.endif
; determine if stack is already enabled. We are using the DefType MSR for this determination.
; It is =0 after reset; CAR setup sets it to enable the MTRRs
mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
.if (!(eax & CR0_MASK))
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
.if (eax & MSR_MASK)
bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
.endif
.endif
; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
mov ebx, esi ; Get my Node/Core info
xor bl, bl
shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
add ah, bh
mov ebx, eax ; Save PCI address for Base/Limit pair
mov dx, 0CF8h
out dx, eax
add dx, 4
xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
out dx, eax ; DRAM Limit = node0, no interleave
mov eax, ebx
sub eax, 4 ; Now point to the Base register
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 00000003h ; Set the read and write enable bits
out dx, eax ; DRAM Base = 0x0000, R/W
AMD_ENABLE_STACK_FAMILY_HOOK
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
_WRMSR
mov eax, esi
bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
.if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
.if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
; Clear all variable and Fixed MTRRs for non-shared cores
mov ecx, AMD_MTRR_VARIABLE_BASE0
xor eax, eax
xor edx, edx
.while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
_WRMSR
inc cl
.endw
mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
_WRMSR
mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
_WRMSR
mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
_WRMSR
mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
; - not strictly needed since the FixedMTRRs take presedence.
mov eax, (16 * 1024 * 1024)
mov ecx, TOP_MEM ; MSR:C001_001A
_WRMSR
.endif ; End Is_Primary
.endif ; End Stack_ReEntry
; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor eax, eax
xor edx, edx
mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
.while (cl != 1Ah)
_WRMSR
inc cl
.endw
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
; To prevent speculative reads from causing an eviction, the unused cache ranges are set
; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
; Note: some core stack regions will share an MTRR since the control granularity is much
; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
; space covered by the MTRR when parseling out cache space for the various uses. In some cases
; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
;
; Outcome of this block is that: (Note the MTRR map at the top of the file)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
;
mov eax, esi ; Load Flags, node, core
.if (al == 0) ; Is a core 0?
.if (ah == 0) ; Is Node 0? (BSP)
; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h))
bt eax, FLAG_FORCE_32K_STACK
.if (carry?)
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h))
.endif
mov ebp, BSP_STACK_BASE_ADDR
.else ; node 1 to 7, core0
; Is a Core0 of secondary node, assign 16K stacks
mov bx, AMD_MTRR_FIX16k_80000
shl ebx, 16 ;
mov bh, ah ; Node# is used as slot#
mov bl, (CORE0_STACK_SIZE / 1000h)
mov al, ah ; Base = (Node# * Size);
mul bl ;
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE0_STACK_BASE_ADDR
mov ebp, eax
.endif
.else ;core 1 thru core 7
; Is core 1-7 of any node, assign 4K stacks
mov al, 8 ; CoreIndex = ( (Node# * 8) ...
mul ah ;
mov bx, si ;
add al, bl ; ... + Core#);
mov bx, AMD_MTRR_FIX64k_00000
shl ebx, 16 ;
mov bh, al ; Slot# = (CoreIndex / 16) + 4;
shr bh, 4 ;
add bh, 4 ;
mov bl, (CORE1_STACK_SIZE / 1000h)
mul bl ; Base = ( (CoreIndex * Size) ...
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
mov ebp, eax
.endif
; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
mov cl, bh ; ShiftCount = ((slot# ...
and cl, 03h ; ... % 4) ...
shl cl, 3 ; ... * 8);
shl edi, cl ; Cache type is now in correct position
ror ebx, 16 ; Get the MTRR address
movzx ecx, bx ;
rol ebx, 16 ; Put slot# & size back in BX
_RDMSR ; Read-modify-write the MSR
.if (bh < 4) ; Is value in lower or upper half of MSR?
or eax, edi ;
.else ;
or edx, edi ;
.endif ;
_WRMSR ;
; Enable MTRR defaults as UC type
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Read-modify-write the MSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Close the modification window on the Fixed MTRRs
mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, CR0_PG ; Make sure paging is disabled
btr eax, CR0_CD ; Clear CR0 NW and CD
btr eax, CR0_NW
mov CR0, eax
; Use the Stack Base & size to calculate SS and ESP values
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
;
mov esp, ebp ; Initialize the stack pointer
mov edi, esp ; Copy the stack start to edi
movzx bx, bl
movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
shl ebx, 12 ; Make size full byte count (* 4K)
add esp, ebx ; Set the Stack Pointer as full linear address
sub esp, 4
;
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - 32b start address of stack block
; ebx - size of stack block
; esp - 32b linear stack pointer
;
; Determine mode for SS base;
mov ecx, CR0 ; Check for 32-bit protect mode
bt ecx, CR0_PE ;
.if (!carry?) ; PE=0 means real mode
mov cx, cs ;
.if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
; alter SS:ESP for 16b Real Mode:
mov eax, edi ;
shr eax, 4 ; Create a Real Mode segment for ss, ds, es
mov ss, ax ;
mov ds, ax ;
mov es, ax ;
shl eax, 4 ;
sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
mov esp, ebx ; Make SP an offset from SS
sub esp, 4 ;
.endif ; endif
; else
; Default is to use Protected 32b Mode
.endif
;
; Clear The Stack
; Now that we have set the location and the MTRRs, initialize the cache by
; reading then writing to zero all of the stack area.
; review:
; ss - Stack base
; esp - stack pointer
; ebx - size of stack block
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - address of start of stack block
;
shr ebx, 2 ;
mov cx, bx ; set cx for size count of DWORDS
; Check our flags - Don't clear an existing stack
.if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
cld
mov esi, edi
rep lods DWORD PTR [esi] ; Pre-load the range
xor eax, eax
mov cx, bx
mov esi, edi ; Preserve base for push on stack
rep stos DWORD PTR [edi] ; Clear the range
mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
shl ebx, 2 ; Put stack size and base
push ebx ; in top of stack
push esi
mov ecx, ebx ; Return size of stack in bytes
mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
.else
movzx ecx, cx
shl ecx, 2 ; Return size of stack, in bytes
mov edx, CPU_EVENT_STACK_REENTRY
mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
.endif
AmdEnableStackExit:
movd ebx, mm0 ; Restore return address
movd ebp, mm1
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_SUCCESS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp, mmx5
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; Save return address
; get node/core/flags of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
_WRMSR
; Set lower 640K MTRRs for Write-Back memory caching
mov ecx, AMD_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR ; 0 - 512K = WB Mem
mov ecx, AMD_MTRR_FIX16k_80000
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
mov ebx, esp ; restore return address (ebx)
xor eax, eax
ENDM

688
src/vendorcode/amd/agesa/f15tn/Legacy/PlatformMemoryConfiguration.inc
View File

@ -1,688 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
;
; ****************************************************************************
; *
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
LR_DIMM0 EQU 0001h
LR_DIMM1 EQU 0010h
LR_DIMM2 EQU 0100h
LR_DIMM3 EQU 1000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
; <
; < CS POPULATION MASKS
;
CS_ANY_ EQU 0FFh
CS0_ EQU 01h
CS1_ EQU 02h
CS2_ EQU 04h
CS3_ EQU 08h
CS4_ EQU 10h
CS5_ EQU 20h
CS6_ EQU 40h
CS7_ EQU 80h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
;
; DIMM VOLTAGE MASK
;
VOLT_ANY_ EQU 0FFh
VOLT1_5_ EQU 01h
VOLT1_35_ EQU 02h
VOLT1_25_ EQU 04h
;
; NOT APPLICIABLE
;
NA_ EQU 00h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel
PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; **********************************
; * TABLE DRIVEN PSO SPECIFIC ENTRIES
; **********************************
; Condition descriptor
PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
; Overriding entry types
PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
;del PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training
PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
DB PSO_CPU_FAMILY_TO_OVERRIDE
DB 4
DD CpuFamilyRevision
ENDM
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 7
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ
DB PSO_MAX_SOLDERED_DOWN_DIMMS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfSolderedDownDimmsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 4
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 7
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 12
DB SocketID
DB ChannelID
DB DimmID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 21
DB SocketID
DB ChannelID
DB DimmID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 4
DB ANY_SOCKET
DB ANY_CHANNEL
DB ALL_DIMMS
DB 1
ENDM
MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
DB PSO_MIN_RD_WR_DATAEYE_WIDTH
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB MinRdDataeyeWidth
DB MinWrDataeyeWidth
ENDM
MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
DB PSO_MEMORY_POWER_POLICY
DB 4
DB ANY_SOCKET
DB ANY_CHANNEL
DB ALL_DIMMS
DB PowerPolicy
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
; *****************************************************************************************
; *
; * TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************
; Configuration sub-descriptors
CONFIG_GENERAL EQU 0
CONFIG_SPEEDLIMIT EQU 1
CONFIG_RC2IBT EQU 2
CONFIG_DONT_CARE EQU 3
Config_Type TEXTEQU <DWORD>
;
; Configuration Macros
;
TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
DB PSO_TBLDRV_CONFIG
DB 9
DB CONFIG_GENERAL
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
ENDM
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
DB PSO_TBLDRV_CONFIG
DB 7
DB CONFIG_SPEEDLIMIT
DB DimmPerCH
DB Dimms
DB NumOfSR
DB NumOfDR
DB NumOfQR
DB NumOfLRDimm
ENDM
TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
DB PSO_TBLDRV_CONFIG
DB 10
DB CONFIG_RC2IBT
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
DB NumOfReg
ENDM
;
; Overriding Macros
;
TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
DB PSO_TBLDRV_SPEEDLIMIT
DB 6
DW SpeedLimit1_5
DW SpeedLimit1_35
DW SpeedLimit1_25
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
DB PSO_TBLDRV_ODT_RTTNOM
DB 2
DB TgtCS
DB RttNom
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
DB PSO_TBLDRV_ODT_RTTWR
DB 2
DB TgtCS
DB RttWr
ENDM
TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
DB PSO_TBLDRV_ODTPATTERN
DB 16
DD RdODTCSHigh
DD RdODTCSLow
DD WrODTCSHigh
DD WrODTCSLow
ENDM
TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
DB PSO_TBLDRV_ADDRTMG
DB 4
DD AddrTmg
ENDM
TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
DB PSO_TBLDRV_ODCCTRL
DB 4
DD OdcCtrl
ENDM
TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
DB PSO_TBLDRV_SLOWACCMODE
DB 1
DB SlowAccMode
ENDM
TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
DB PSO_TBLDRV_RC2_IBT
DB 2
DB TgtDimm
DB IBT
ENDM
TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_CL
DB 3
DB RegValOfTcl
DB MR0CL13
DB MR0CL0
ENDM
TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_WR
DB 2
DB RegValOfTcl
DB MR0WR
ENDM
TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_RC10_OPSPEED
DB 5
DD Frequency
DB MR10OPSPEED
ENDM
TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
DB PSO_TBLDRV_LRDIMM_IBT
DB 4
DB F0RC8
DB F1RC0
DB F1RC1
DB F1RC2
ENDM
;del TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ
;del DB PSO_TBLDRV_2D_TRAINING
;del DB 1
;del DB Training2dMode
;del ENDM
;
; Macros for removing entries
;
INVALID_CONFIG_FLAG EQU 8000h
TBLDRV_INVALID_CONFIG MACRO
DB PSO_TBLDRV_INVALID_TYPE
DB 0
ENDM
; *****************************************************************************************
; *
; * END OF TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************

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src/vendorcode/amd/agesa/f15tn/Legacy/Proc/arch2008.asm
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src/vendorcode/amd/agesa/f15tn/Legacy/agesa.inc
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src/vendorcode/amd/agesa/f15tn/Legacy/amd.inc
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@ -1,461 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
;
; ****************************************************************************
; *
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

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src/vendorcode/amd/agesa/f15tn/Legacy/bridge32.inc
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@ -1,576 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
;
; ****************************************************************************
;
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

602
src/vendorcode/amd/agesa/f15tn/Lib/x64/amdlib64.asm
View File

@ -1,602 +0,0 @@
;/**
; * @file
; *
; * Agesa library 64bit
; *
; * Contains AMD AGESA Library
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Lib
; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.code
;/*++
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO byte
; *
; * @param[in] CX IO port address
; * @param[in] DL IO port Value
; */
PUBLIC WriteIo8
WriteIo8 PROC
mov al, dl
mov dx, cx
out dx, al
ret
WriteIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO word
; *
; * @param[in] CX IO port address
; * @param[in] DX IO port Value
; */
PUBLIC WriteIo16
WriteIo16 PROC
mov ax, dx
mov dx, cx
out dx, ax
ret
WriteIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write IO dword
; *
; * @param[in] CX IO port address
; * @param[in] EDX IO port Value
; */
PUBLIC WriteIo32
WriteIo32 PROC
mov eax, edx
mov dx, cx
out dx, eax
ret
WriteIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO byte
; *
; * @param[in] CX IO port address
; * @retval AL IO port Value
; */
PUBLIC ReadIo8
ReadIo8 PROC
mov dx, cx
in al, dx
ret
ReadIo8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO word
; *
; * @param[in] CX IO port address
; * @retval AX IO port Value
; */
PUBLIC ReadIo16
ReadIo16 PROC
mov dx, cx
in ax, dx
ret
ReadIo16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read IO dword
; *
; * @param[in] CX IO port address
; * @retval EAX IO port Value
; */
PUBLIC ReadIo32
ReadIo32 PROC
mov dx, cx
in eax, dx
ret
ReadIo32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrRead
LibAmdMsrRead PROC
push rsi
mov rsi, rdx
rdmsr
mov [rsi], eax
mov [rsi+4], edx
pop rsi
ret
LibAmdMsrRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write MSR
; *
; * @param[in] RCX MSR Address
; * @param[in] RDX Pointer to data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdMsrWrite
LibAmdMsrWrite PROC
push rsi
mov rsi, rdx
mov eax, [rsi]
and rax, 0ffffffffh
mov edx, [rsi+4]
and rdx, 0ffffffffh
wrmsr
pop rsi
ret
LibAmdMsrWrite ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read CPUID
; *
; * @param[in] RCX CPUID function
; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
; * @param[in] R8D ConfigPtr (Optional)
; */
PUBLIC LibAmdCpuidRead
LibAmdCpuidRead PROC
push rbx
push rsi
mov rsi, rdx
mov rax, rcx
cpuid
mov [rsi], eax
mov [rsi+4], ebx
mov [rsi+8], ecx
mov [rsi+12],edx
pop rsi
pop rbx
ret
LibAmdCpuidRead ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read TSC
; *
; *
; * @retval RAX Time stamp counter value
; */
PUBLIC ReadTSC
ReadTSC PROC
rdtsc
and rax, 0ffffffffh
shl rdx, 32
or rax, rdx
ret
ReadTSC ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO byte
; *
; * @param[in] RCX - Memory Address
; * @retval Memory byte at given address
; */
PUBLIC Read64Mem8
Read64Mem8 PROC
xor rax, rax
mov al, [rcx]
ret
Read64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO word
; *
; * @param[in] RCX - Memory Address
; * @retval Memory word at given address
; */
PUBLIC Read64Mem16
Read64Mem16 PROC
xor rax, rax
mov ax, [rcx]
ret
Read64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read memory/MMIO dword
; *
; * @param[in] RCX - Memory Address
; * @retval Memory dword at given address
; */
PUBLIC Read64Mem32
Read64Mem32 PROC
xor rax, rax
mov eax, [rcx]
ret
Read64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO byte
; *
; * @param[in] RCX Memory Address
; * @param[in] DL Value to write
; */
PUBLIC Write64Mem8
Write64Mem8 PROC
xor rax, rax
mov rax, rdx
mov [rcx], al
ret
Write64Mem8 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO word
; *
; * @param[in] RCX Memory Address
; * @param[in] DX Value to write
; */
PUBLIC Write64Mem16
Write64Mem16 PROC
xor rax, rax
mov rax, rdx
mov [rcx], ax
ret
Write64Mem16 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write memory/MMIO dword
; *
; * @param[in] RCX Memory Address
; * @param[in] EDX Value to write
; */
PUBLIC Write64Mem32
Write64Mem32 PROC
xor rax, rax
mov rax, rdx
mov [rcx], eax
ret
Write64Mem32 ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Read various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Pointer to value
; */
PUBLIC LibAmdReadCpuReg
LibAmdReadCpuReg PROC
push rax
xor rax, rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
jmp RegRead
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
jmp RegRead
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
jmp RegRead
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
jmp RegRead
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
jmp RegRead
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
jmp RegRead
Reg17h:
cmp cl, 17h
jne RegRead
mov rax, dr7
RegRead:
mov [rdx], eax
pop rax
ret
LibAmdReadCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write various CPU registers
; *
; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
; * @param[in] RDX Value to write
; */
PUBLIC LibAmdWriteCpuReg
LibAmdWriteCpuReg PROC
push rax
Reg00h:
cmp cl, 00h
jne Reg04h
mov rax, cr0
mov eax, edx
mov cr0, rax
jmp Done
Reg04h:
cmp cl, 04h
jne Reg10h
mov rax, cr4
mov eax, edx
mov cr4, rax
jmp Done
Reg10h:
cmp cl, 10h
jne Reg11h
mov rax, dr0
mov eax, edx
mov dr0, rax
jmp Done
Reg11h:
cmp cl, 11h
jne Reg12h
mov rax, dr1
mov eax, edx
mov dr1, rax
jmp Done
Reg12h:
cmp cl, 12h
jne Reg13h
mov rax, dr2
mov eax, edx
mov dr2, rax
jmp Done
Reg13h:
cmp cl, 13h
jne Reg17h
mov rax, dr3
mov eax, edx
mov dr3, rax
jmp Done
Reg17h:
cmp cl, 17h
jne Done
mov rax, dr7
mov eax, edx
mov dr7, rax
Done:
pop rax
ret
LibAmdWriteCpuReg ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Write back invalidate caches using wbinvd.
; *
; *
; *
; */
PUBLIC LibAmdWriteBackInvalidateCache
LibAmdWriteBackInvalidateCache PROC
wbinvd
ret
LibAmdWriteBackInvalidateCache ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
PUBLIC StopHere
StopHere PROC
@@:
jmp short @b
StopHere ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Enter debugger on SimNow
; *
; *
; *
; */
PUBLIC LibAmdSimNowEnterDebugger
LibAmdSimNowEnterDebugger PROC
pushfq
mov rax, 0BACCD00Bh ; Backdoor in SimNow
mov rbx, 2 ; Select breakpoint feature
cpuid
@@:
jmp short @b
popfq
ret
LibAmdSimNowEnterDebugger ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * IDS IO port write
; *
; * @param[in] ECX IO Port Address
; * @param[in] EDX Value to write
; * @param[in] R8D IDS flags
; *
; */
PUBLIC IdsOutPort
IdsOutPort PROC
push rbx
push rax
mov ebx, r8d
mov eax, edx
mov edx, ecx
out dx, eax
pop rax
pop rbx
ret
IdsOutPort ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Force breakpoint on HDT
; *
; *
; */
PUBLIC LibAmdHDTBreakPoint
LibAmdHDTBreakPoint PROC
push rbx
mov rcx, 0C001100Ah ;bit 0 = HDT redirect
mov rdi, 09C5A203Ah ;Password
rdmsr
and rax, 0ffffffffh
or rax, 1
wrmsr
mov rax, 0B2h ;Marker = B2
db 0F1h ;ICEBP
pop rbx
ret
LibAmdHDTBreakPoint ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most right hand side non-zero bit with
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanForward
LibAmdBitScanForward PROC
bsf eax, ecx
jnz nonZeroSource
mov al,32
nonZeroSource:
ret
LibAmdBitScanForward ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Find the most left hand side non-zero bit.
; *
; * @param[in] ECX Value
; */
PUBLIC LibAmdBitScanReverse
LibAmdBitScanReverse PROC
bsr eax, ecx
jnz nonZeroSource
mov al,0FFh
nonZeroSource:
ret
LibAmdBitScanReverse ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * Flush specified number of cache line
; *
; * @param[in] RCX Physical address to be flushed
; * @param[in] DL number of cachelines to be flushed
; */
PUBLIC LibAmdCLFlush
LibAmdCLFlush PROC
push rax
mov rax, rcx
movzx rcx, dl
@@:
mfence
clflush [rax]
mfence
add rax,64
loop @B
pop rax
ret
LibAmdCLFlush ENDP
;/*---------------------------------------------------------------------------------------*/
;/**
; * FPU init
; *
; *
; */
PUBLIC LibAmdFinit
LibAmdFinit PROC
finit
ret
LibAmdFinit ENDP
END

361
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt.asm
View File

@ -1,361 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE agesa.inc
INCLUDE cpcarmac.inc
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y A B S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; ExecuteFinalHltInstruction: Disables the stack and performs
; a hlt instruction on an AP.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteFinalHltInstruction
ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
mov esi, HaltFlags
mov edi, ApMtrrSettingList
; Do these special steps in case if the core is part of a compute unit
; Note: The following bits are family specific flags, that gets set during build time,
; and indicates things like "family cache control methodology", etc.
; esi bit0 = 0 -> not a Primary core
; esi bit0 = 1 -> Primary core
; esi bit1 = 0 -> Cache disable
; esi bit1 = 1 -> Cache enable
.if (esi & 2h)
; Set CombineCr0Cd bit
mov ecx, CU_CFG3
_RDMSR
bts edx, (COMBINE_CR0_CD - 32)
_WRMSR
; Clear the CR0.CD bit
mov eax, CR0 ; Make sure cache is enabled for all APs
btr eax, CR0_CD
btr eax, CR0_NW
mov CR0, eax ; Write back to CR0
.else
mov eax, CR0 ; Make sure cache is disabled for all APs
bts eax, CR0_CD ; Disable cache
bts eax, CR0_NW
mov CR0, eax ; Write back to CR0
.endif
.if (esi & 1h)
; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
mov esi, edi ; Get ApMtrrSettingList
; Configure the MTRRs on the AP so
; when it runs remote code it will execute
; out of RAM instead of ROM.
; Disable MTRRs and turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MTRR_VAR_DRAM_EN ; Disable
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
btr eax, MTRR_FIX_DRAM_EN ; Disable
bts eax, SYS_UC_LOCK_EN
_WRMSR
; Setup default values for Fixed-Sized MTRRs
; Set 7FFFh-00000h as WB
mov ecx, AMD_AP_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR
; Set 9FFFFh-80000h also as WB
mov ecx, AMD_AP_MTRR_FIX16k_80000
_WRMSR
; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
mov ecx, AMD_AP_MTRR_FIX16k_A0000
xor eax, eax
xor edx, edx
_WRMSR
; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
xor eax, eax
xor edx, edx
mov ecx, AMD_AP_MTRR_FIX4k_C0000
CDLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_D8000
jbe CDLoop
; Set FFFFFh-E0000h as Uncacheable Memory
mov eax, 18181818h
mov edx, eax
mov ecx, AMD_AP_MTRR_FIX4k_E0000
EFLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_F8000
jbe EFLoop
; If IBV provided settings for Fixed-Sized MTRRs,
; overwrite the default settings.
.if ((esi != 0) && (esi != 0FFFFFFFFh))
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
; While we are not at the end of the list
.while (ecx != CPU_LIST_TERMINAL)
; Ensure that the MSR address is valid for Fixed-Sized MTRRs
.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
_WRMSR
.endif
add esi, sizeof (AP_MTRR_SETTINGS)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
.endw
.endif
; Enable fixed-range and variable-range MTRRs
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Enable Top-of-Memory setting
; Enable use of RdMem/WrMem bits attributes
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MTRR_VAR_DRAM_EN ; Enable
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
bts eax, MTRR_FIX_DRAM_EN ; Enable
_WRMSR
mov esi, (1 SHL FLAG_IS_PRIMARY)
.else ; end if primary core
xor esi, esi
.endif
; Make sure not to touch any Shared MSR from this point on
AMD_DISABLE_STACK_FAMILY_HOOK
bt esi, FLAG_IS_PRIMARY
.if (carry?)
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
.while (cx >= AMD_MTRR_VARIABLE_BASE6)
_WRMSR
dec cx
.endw
.endif
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ret
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteHltInstruction
ExecuteHltInstruction PROC NEAR C
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC NmiHandler
NmiHandler PROC NEAR C
iretd
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC GetCsSelector
GetCsSelector PROC NEAR C, CsSelector:PTR
push ax
push ebx
call FarCallGetCs
mov ebx, CsSelector
mov [ebx], ax
pop ebx
pop ax
ret
GetCsSelector ENDP
;======================================================================
; FarCallGetCs:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
FarCallGetCs PROC FAR PRIVATE
mov ax, ss:[esp + 4]
retf
FarCallGetCs ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC SetIdtr
SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
lidt fword ptr ss:[ebx]
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC GetIdtr
GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
sidt fword ptr ss:[ebx]
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC ExecuteWbinvdInstruction
ExecuteWbinvdInstruction PROC NEAR C
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

173
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahalt64.asm
View File

@ -1,173 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; */
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
text SEGMENT
;======================================================================
; ExecuteFinalHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteFinalHltInstruction PROC PUBLIC
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteHltInstruction PROC PUBLIC
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
NmiHandler PROC PUBLIC
iretq
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
GetCsSelector PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetCsSelector ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
SetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
GetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
ExecuteWbinvdInstruction PROC PUBLIC
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

335
src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm
View File

@ -1,335 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 32bit
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 14305 $ @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
public IdsDelay
IdsDelay PROC NEAR C USES EAX EDX
Local targetedx:dword, targeteax:dword
rdtsc
;set target time
add eax,1500000000
adc edx,0
mov targetedx,edx
mov targeteax,eax
rdtsc
;set "Si!=0" skip below loop
.while(1)
.if(si != 0)
jmp delay_exit
.endif
.if(edx > targetedx)
jmp delay_exit
.elseif (edx == targetedx)
.if(eax > targeteax)
jmp delay_exit
.endif
.endif
rdtsc
.endw
delay_exit:
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC NEAR C filecode:dword
local tmpebx:dword,tmpedx:dword
pushad
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, filecode
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov ebx,0dead0000h
mov edx,filecode
ror edx,16
mov bx,dx
mov dx,0
;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
mov tmpebx,ebx
mov tmpedx,edx
xor eax,eax
mov cl,6
.while((cl != 0) && (si == 0))
.if(cl <= 2)
shld eax,edx,8
shl edx,8
.else
shld eax,ebx,8
shl ebx,8
.endif
out 80h,eax
call IdsDelay
dec cl
.if(cl == 0)
mov cl,6
mov ebx,tmpebx
mov edx,tmpedx
.endif
.endw
popad
xor eax,eax
ret
IdsErrorStop endp
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
IDS_STOP_HERE MACRO
@@:
jmp short @b
ENDM
;======================================================================
; IdsExceptionHandler: Simply performs a jmp $ and IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC _IdsExceptionHandler
PUBLIC _SizeIdtDescriptor
PUBLIC _SizeTotalIdtDescriptors
; Size of each exception MUST be the same
Exception00:
push eax
mov al, 00h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception01:
push eax
mov al, 01h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception02:
push eax
mov al, 02h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception03:
push eax
mov al, 03h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception04:
push eax
mov al, 04h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception05:
push eax
mov al, 05h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception06:
push eax
mov al, 06h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception07:
push eax
mov al, 07h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception08:
push eax
mov al, 08h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception09:
push eax
mov al, 09h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception10:
push eax
mov al, 10h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception11:
push eax
mov al, 11h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception12:
push eax
mov al, 12h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception13:
push eax
mov al, 13h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception14:
push eax
mov al, 14h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception15:
push eax
mov al, 15h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception16:
push eax
mov al, 16h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception17:
push eax
mov al, 17h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception18:
push eax
mov al, 18h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception19:
push eax
mov al, 19h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception20:
push eax
mov al, 20h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception21:
push eax
mov al, 21h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception22:
push eax
mov al, 22h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception23:
push eax
mov al, 23h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception24:
push eax
mov al, 24h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception25:
push eax
mov al, 25h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception26:
push eax
mov al, 26
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception27:
push eax
mov al, 27h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception28:
push eax
mov al, 28h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception29:
push eax
mov al, 29h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception30:
push eax
mov al, 30h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception31:
push eax
mov al, 31h
jmp near ptr CommonHandler
CommonHandler:
out 80h, al
pop eax
IDS_STOP_HERE
iretd
_IdsExceptionHandler dq offset Exception00
_SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
END

342
src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm
View File

@ -1,342 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 64bit
; *
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 14126 $ @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.code
IdsDelay PROC
push rax
push rdx
push rbx
xor rax,rax
xor rdx,rdx
rdtsc
;set target time
add eax,1500000000
adc edx,0
shl rdx,32
add rdx,rax
mov rbx,rdx
;rbx store the target
;set "Si!=0" skip below loop
__loop:
cmp si,0
jnz __loopexit
rdtsc
shl rdx,32
add rdx,rax
cmp rdx,rbx
jae __loopexit
jmp __loop
__loopexit:
pop rbx
pop rdx
pop rax
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC
;As x64 calling convention RCX is used as input parameters
push rcx
push rbx
push si
push dx
push rbx
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, ecx
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov rax,0dead00000000h
or rcx,rax
;rcx= 0dead__FILECODE
shl rcx,16
;rcx= 0dead__FILECODE__0000
mov rbx,rcx
xor rax,rax
mov dl,6
IdsErrorStopLoop:
cmp dl,0
jz IdsErrorStopExit
cmp si,0
jnz IdsErrorStopExit
shld rax,rcx,8
shl rcx,8
out 80h,eax
call IdsDelay
dec dl
cmp dl,0
jnz _nextloop
mov dl,6
mov rcx,rbx
_nextloop:
jmp IdsErrorStopLoop
IdsErrorStopExit:
pop rbx
pop dx
pop si
pop rbx
pop rcx
xor rax,rax
ret
IdsErrorStop endp
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
IDS_STOP_HERE MACRO
@@:
jmp short @b
ENDM
;======================================================================
; IdsExceptionHandler: Simply performs a jmp $ and IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC IdsExceptionHandler
PUBLIC SizeIdtDescriptor
PUBLIC SizeTotalIdtDescriptors
; Size of each exception MUST be the same
Exception00:
push rax
mov al, 00h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception01:
push rax
mov al, 01h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception02:
push rax
mov al, 02h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception03:
push rax
mov al, 03h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception04:
push rax
mov al, 04h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception05:
push rax
mov al, 05h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception06:
push rax
mov al, 06h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception07:
push rax
mov al, 07h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception08:
push rax
mov al, 08h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception09:
push rax
mov al, 09h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception10:
push rax
mov al, 10h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception11:
push rax
mov al, 11h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception12:
push rax
mov al, 12h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception13:
push rax
mov al, 13h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception14:
push rax
mov al, 14h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception15:
push rax
mov al, 15h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception16:
push rax
mov al, 16h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception17:
push rax
mov al, 17h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception18:
push rax
mov al, 18h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception19:
push rax
mov al, 19h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception20:
push rax
mov al, 20h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception21:
push rax
mov al, 21h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception22:
push rax
mov al, 22h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception23:
push rax
mov al, 23h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception24:
push rax
mov al, 24h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception25:
push rax
mov al, 25h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception26:
push rax
mov al, 26
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception27:
push rax
mov al, 27h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception28:
push rax
mov al, 28h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception29:
push rax
mov al, 29h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception30:
push rax
mov al, 30h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception31:
push rax
mov al, 31h
jmp near ptr CommonHandler
CommonHandler:
out 80h, al
pop rax
IDS_STOP_HERE
iretq
IdsExceptionHandler dq offset Exception00
SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
END

496
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mu.asm
View File

@ -1,496 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Description: Main memory controller system configuration for AGESA
;
;
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;memUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written
;
; Out:
;
; All registers preserved.
;===============================================================================
MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemUOutPort ENDP
;----------------------------------------------------------------------------
; _SFENCE();
;
_SFENCE macro
db 0Fh,0AEh,0F8h
endm
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemUWriteCachelines:
; Write a test pattern to DRAM
;
; In: Pattern - pointer to the write pattern
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
xor ecx, ecx
mov cx,ClCount
shl ecx,2
@@:
db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemUWriteCachelines ENDP
;===============================================================================
;MemUReadCachelines:
;
; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
;pattern is a stress pattern which exercises both ISI and crosstalk. The number
;of cache lines to fill is dependent on DCT width mode and burstlength.
;
; In: Buffer - pointer to a buffer where read data will be stored
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL Count:BYTE
pushad
; First, issue continuous dummy reads to fill up the cache
mov eax,Address
.if (ClCount > 18)
mov cx,ClCount
shr cx,4
mov Count,cl
.while (Count != 0)
push eax
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
pop eax
add eax,(16*64) ;Next 16CL
dec Count
.endw
.else
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
.if(ClCount == 1)
_MFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
.elseif(ClCount == 3)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
.elseif(ClCount == 6)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
.elseif(ClCount == 9)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
.elseif(ClCount == 18)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
mov eax,fs:[edx] ;TestAddr+16 cache lines
_MFENCE
mov eax,fs:[edx+64] ;TestAddr+17 cache lines
_MFENCE
.endif
.endif
_MFENCE
; Then, copy data to buffer
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
xor ecx, ecx
mov cx,ClCount
shl ecx,6
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemUReadCachelines ENDP
;===============================================================================
;MemUDummyCLRead:
;
; Perform a single cache line read from a given physical address.
;
; In: Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
_SFENCE
pushad
mov eax,Address
mov dl,fs:[eax]
popad
ret
MemUDummyCLRead ENDP
;===============================================================================
;MemUFlushPattern:
;
; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
;to ensure cache miss on the next read training.
;
; In: Address - Physical address to be flushed
; ClCount - number of cachelines to be flushed
; Out:
;
;All registers preserved.
;===============================================================================
MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
pushad
mov edi,Address
movzx ecx,ClCount
@@:
_MFENCE ; Force strong ordering of clflush
db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
_MFENCE
add edi,64
loop @B
popad
ret
MemUFlushPattern ENDP
;===============================================================================
;MemUGetWrLvNblErr:
; Read ClCount number of cachelines then return the bitmap that indicates
; the write leveling result of each byte lane.
;
; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
; Address - Physical address to be sampled
; ClCount - number of cachelines to be read
;
; OUT: ErrBitmap - WL result
;
;All registers preserved
;===============================================================================
MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL ZeroCount[32]:WORD
pushad
mov esi,Address
_EXECFENCE
;Cache fill
movzx ecx,ClCount
@@:
mov eax,fs:[esi]
add esi,64
loop @B
_MFENCE
; Then, count the number of 0's
;push es
;push ss
;pop es
lea edi,ZeroCount
mov cx,SIZEOF ZeroCount
mov al,0
rep stosb
;pop es
mov esi,Address
lea edi,ZeroCount
mov cx,ClCount
shl cx,6
.while(cx > 0)
mov al,fs:[esi]
test al,00Fh ;check lower nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
test al,0F0h ;check upper nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
inc esi
dec cx
test cx,07h
.if(ZERO?)
sub edi,(16*2)
sub cx,8
add esi,8
.endif
.endw
; Then, average and compress data to error bits
lea esi,ZeroCount
mov dx,ClCount
shl dx,1
xor eax,eax
xor ecx,ecx
mov cl,0
.while(cl<16)
.if(WORD PTR [esi] < dx)
bts eax,ecx
.endif
add esi,2
inc cl
.endw
xor edx,edx
mov dx,WORD PTR ErrBitmap
mov [edx], ax
popad
ret
MemUGetWrLvNblErr ENDP
;===============================================================================
;AlignPointerTo16Byte:
; Modifies BufferPtr to be 16 byte aligned
;
; In: BufferPtrPtr - Pointer to buffer pointer
; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
;
;All registers preserved.
;===============================================================================
AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
push edx
push eax
mov edx, BufferPtrPtr
mov eax, [edx]
add eax, 16
and ax, 0FFF0h
mov [edx], eax
pop eax
pop edx
ret
AlignPointerTo16Byte ENDP
;===============================================================================
;MemUMFenceInstr:
; Serialize instruction
;
; In:
; Out:
;
;All registers preserved.
;===============================================================================
MemUMFenceInstr PROC CALLCONV PUBLIC
_MFENCE
ret
MemUMFenceInstr ENDP
END

456
src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
View File

@ -1,456 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
.mmx
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; EBX = Return address (preserved)
;
; Out:
; SS:ESP - Our new private stack location
;
; EAX = AGESA_STATUS
; EDX = Return status code if EAX contains a return code of higher
; severity than AGESA_SUCCESS
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processor cores
; Preserved:
; ebx ebp
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es, ss, esp
; mmx0, mmx1, mmx5
;
; Description:
; Fixed MTRR address allocation to cores:
; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
; There is a max of 1 BSP, 7 core0s and 56 other cores.
; Although each core has it's own cache storage, they share the address space. Each core must
; be assigned a private and unique address space for its stack. To support legacy systems,
; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
;
; 80000h 40000h 00000h
; +----------+----------+----------+----------+----------+----------+----------+----------+
; 64K | | | | | | | | | 64K ea
; ea +----------+----------+----------+----------+----------+----------+----------+----------+
; | MTRR 0000_0250 MTRRfix64K_00000 |
; +----------+----------+----------+----------+----------+----------+----------+----------+
; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
; +----------+----------+----------+----------+----------+----------+----------+----------+
;
; C0000h B0000h A0000h 90000h 80000h
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;16K | | | | | | | | | | | | | | | | |
; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;
; E0000h D0000h C0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;
; 100000h F0000h E0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;======================================================================
AMD_ENABLE_STACK MACRO
local AmdEnableStackExit
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
movd mm0, ebx ; Put return address in a safe place
movd mm1, ebp ; Save some other user registers
; get node id and core id of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
; If we detected an unknown processor family or core combination, return AGESA_FATAL.
.if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.endif
; determine if stack is already enabled. We are using the DefType MSR for this determination.
; It is =0 after reset; CAR setup sets it to enable the MTRRs
mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
.if (!(eax & CR0_MASK))
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
.if (eax & MSR_MASK)
bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
.endif
.endif
; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
mov ebx, esi ; Get my Node/Core info
xor bl, bl
shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
add ah, bh
mov ebx, eax ; Save PCI address for Base/Limit pair
mov dx, 0CF8h
out dx, eax
add dx, 4
xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
out dx, eax ; DRAM Limit = node0, no interleave
mov eax, ebx
sub eax, 4 ; Now point to the Base register
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 00000003h ; Set the read and write enable bits
out dx, eax ; DRAM Base = 0x0000, R/W
AMD_ENABLE_STACK_FAMILY_HOOK
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
_WRMSR
mov eax, esi
bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
.if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
.if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
; Clear all variable and Fixed MTRRs for non-shared cores
mov ecx, AMD_MTRR_VARIABLE_BASE0
xor eax, eax
xor edx, edx
.while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
_WRMSR
inc cl
.endw
mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
_WRMSR
mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
_WRMSR
mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
_WRMSR
mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
; - not strictly needed since the FixedMTRRs take presedence.
mov eax, (16 * 1024 * 1024)
mov ecx, TOP_MEM ; MSR:C001_001A
_WRMSR
.endif ; End Is_Primary
.endif ; End Stack_ReEntry
; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor eax, eax
xor edx, edx
mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
.while (cl != 1Ah)
_WRMSR
inc cl
.endw
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
; To prevent speculative reads from causing an eviction, the unused cache ranges are set
; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
; Note: some core stack regions will share an MTRR since the control granularity is much
; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
; space covered by the MTRR when parseling out cache space for the various uses. In some cases
; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
;
; Outcome of this block is that: (Note the MTRR map at the top of the file)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
;
mov eax, esi ; Load Flags, node, core
.if (al == 0) ; Is a core 0?
.if (ah == 0) ; Is Node 0? (BSP)
; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h))
bt eax, FLAG_FORCE_32K_STACK
.if (carry?)
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h))
.endif
mov ebp, BSP_STACK_BASE_ADDR
.else ; node 1 to 7, core0
; Is a Core0 of secondary node, assign 16K stacks
mov bx, AMD_MTRR_FIX16k_80000
shl ebx, 16 ;
mov bh, ah ; Node# is used as slot#
mov bl, (CORE0_STACK_SIZE / 1000h)
mov al, ah ; Base = (Node# * Size);
mul bl ;
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE0_STACK_BASE_ADDR
mov ebp, eax
.endif
.else ;core 1 thru core 7
; Is core 1-7 of any node, assign 4K stacks
mov al, 8 ; CoreIndex = ( (Node# * 8) ...
mul ah ;
mov bx, si ;
add al, bl ; ... + Core#);
mov bx, AMD_MTRR_FIX64k_00000
shl ebx, 16 ;
mov bh, al ; Slot# = (CoreIndex / 16) + 4;
shr bh, 4 ;
add bh, 4 ;
mov bl, (CORE1_STACK_SIZE / 1000h)
mul bl ; Base = ( (CoreIndex * Size) ...
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
mov ebp, eax
.endif
; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
mov cl, bh ; ShiftCount = ((slot# ...
and cl, 03h ; ... % 4) ...
shl cl, 3 ; ... * 8);
shl edi, cl ; Cache type is now in correct position
ror ebx, 16 ; Get the MTRR address
movzx ecx, bx ;
rol ebx, 16 ; Put slot# & size back in BX
_RDMSR ; Read-modify-write the MSR
.if (bh < 4) ; Is value in lower or upper half of MSR?
or eax, edi ;
.else ;
or edx, edi ;
.endif ;
_WRMSR ;
; Enable MTRR defaults as UC type
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Read-modify-write the MSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Close the modification window on the Fixed MTRRs
mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, CR0_PG ; Make sure paging is disabled
btr eax, CR0_CD ; Clear CR0 NW and CD
btr eax, CR0_NW
mov CR0, eax
; Use the Stack Base & size to calculate SS and ESP values
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
;
mov esp, ebp ; Initialize the stack pointer
mov edi, esp ; Copy the stack start to edi
movzx bx, bl
movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
shl ebx, 12 ; Make size full byte count (* 4K)
add esp, ebx ; Set the Stack Pointer as full linear address
sub esp, 4
;
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - 32b start address of stack block
; ebx - size of stack block
; esp - 32b linear stack pointer
;
; Determine mode for SS base;
mov ecx, CR0 ; Check for 32-bit protect mode
bt ecx, CR0_PE ;
.if (!carry?) ; PE=0 means real mode
mov cx, cs ;
.if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
; alter SS:ESP for 16b Real Mode:
mov eax, edi ;
shr eax, 4 ; Create a Real Mode segment for ss, ds, es
mov ss, ax ;
mov ds, ax ;
mov es, ax ;
shl eax, 4 ;
sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
mov esp, ebx ; Make SP an offset from SS
sub esp, 4 ;
.endif ; endif
; else
; Default is to use Protected 32b Mode
.endif
;
; Clear The Stack
; Now that we have set the location and the MTRRs, initialize the cache by
; reading then writing to zero all of the stack area.
; review:
; ss - Stack base
; esp - stack pointer
; ebx - size of stack block
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - address of start of stack block
;
shr ebx, 2 ;
mov cx, bx ; set cx for size count of DWORDS
; Check our flags - Don't clear an existing stack
.if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
cld
mov esi, edi
rep lods DWORD PTR [esi] ; Pre-load the range
xor eax, eax
mov cx, bx
mov esi, edi ; Preserve base for push on stack
rep stos DWORD PTR [edi] ; Clear the range
mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
shl ebx, 2 ; Put stack size and base
push ebx ; in top of stack
push esi
mov ecx, ebx ; Return size of stack in bytes
mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
.else
movzx ecx, cx
shl ecx, 2 ; Return size of stack, in bytes
mov edx, CPU_EVENT_STACK_REENTRY
mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
.endif
AmdEnableStackExit:
movd ebx, mm0 ; Restore return address
movd ebp, mm1
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_SUCCESS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp, mmx5
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; Save return address
; get node/core/flags of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
_WRMSR
; Set lower 640K MTRRs for Write-Back memory caching
mov ecx, AMD_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR ; 0 - 512K = WB Mem
mov ecx, AMD_MTRR_FIX16k_80000
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
mov ebx, esp ; restore return address (ebx)
xor eax, eax
ENDM

701
src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc
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@ -1,701 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
;
; ****************************************************************************
; *
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
LR_DIMM0 EQU 0001h
LR_DIMM1 EQU 0010h
LR_DIMM2 EQU 0100h
LR_DIMM3 EQU 1000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
; <
; < CS POPULATION MASKS
;
CS_ANY_ EQU 0FFh
CS0_ EQU 01h
CS1_ EQU 02h
CS2_ EQU 04h
CS3_ EQU 08h
CS4_ EQU 10h
CS5_ EQU 20h
CS6_ EQU 40h
CS7_ EQU 80h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
;
; DIMM VOLTAGE MASK
;
VOLT_ANY_ EQU 0FFh
VOLT1_5_ EQU 01h
VOLT1_35_ EQU 02h
VOLT1_25_ EQU 04h
;
; NOT APPLICIABLE
;
NA_ EQU 00h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
;
; MOTHER BOARD DESIGN LAYERS MASKS
; Indicates the layer design of mother board
;
LAYERS_4 EQU 0h
LAYERS_6 EQU 01h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
PSO_MIN_RD_WR_DATAEYE_WIDTH EQU 17 ; < Min RD/WR dataeye width
PSO_CPU_FAMILY_TO_OVERRIDE EQU 18 ; < CPU family signature to tell following PSO macros are CPU family dependent
PSO_MAX_SOLDERED_DOWN_DIMMS EQU 19 ; < Max Soldered-down Dimms per channel
PSO_MEMORY_POWER_POLICY EQU 20 ; < Memory power policy override
PSO_MOTHER_BOARD_LAYERS EQU 21 ; < Mother board layer design
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; **********************************
; * TABLE DRIVEN PSO SPECIFIC ENTRIES
; **********************************
; Condition descriptor
PSO_TBLDRV_CONFIG EQU 200 ; < Configuration Descriptor
; Overriding entry types
PSO_TBLDRV_START EQU 210 ; < Start of Table Driven Overriding Entry Types
PSO_TBLDRV_SPEEDLIMIT EQU 210 ; < Speed Limit
PSO_TBLDRV_ODT_RTTNOM EQU 211 ; < RttNom
PSO_TBLDRV_ODT_RTTWR EQU 212 ; < RttWr
PSO_TBLDRV_ODTPATTERN EQU 213 ; < Odt Patterns
PSO_TBLDRV_ADDRTMG EQU 214 ; < Address/Timing values
PSO_TBLDRV_ODCCTRL EQU 215 ; < ODC Control values
PSO_TBLDRV_SLOWACCMODE EQU 216 ; < Slow Access Mode
PSO_TBLDRV_MR0_CL EQU 217 ; < MR0[CL]
PSO_TBLDRV_MR0_WR EQU 218 ; < MR0[WR]
PSO_TBLDRV_RC2_IBT EQU 219 ; < RC2[IBT]
PSO_TBLDRV_RC10_OPSPEED EQU 220 ; < RC10[Opearting Speed]
PSO_TBLDRV_LRDIMM_IBT EQU 221 ; < LrDIMM IBT
PSO_TBLDRV_2D_TRAINING EQU 222 ; < 2D training
PSO_TBLDRV_INVALID_TYPE EQU 223 ; < Invalid Type
PSO_TBLDRV_END EQU 223 ; < End of Table Driven Overriding Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CPU_FAMILY_TO_OVERRIDE MACRO CpuFamilyRevision:REQ
DB PSO_CPU_FAMILY_TO_OVERRIDE
DB 4
DD CpuFamilyRevision
ENDM
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 7
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfSolderedDownDimmsPerChannel:REQ
DB PSO_MAX_SOLDERED_DOWN_DIMMS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfSolderedDownDimmsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 4
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 11
DB SocketID
DB ChannelID
DB ALL_DIMMS
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 7
DB SocketID
DB ANY_CHANNEL
DB ALL_DIMMS
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 12
DB SocketID
DB ChannelID
DB DimmID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 21
DB SocketID
DB ChannelID
DB DimmID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
DB 4
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB 1
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 4
DB ANY_SOCKET
DB ANY_CHANNEL
DB ALL_DIMMS
DB 1
ENDM
MIN_RD_WR_DATAEYE_WIDTH MACRO SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
DB PSO_MIN_RD_WR_DATAEYE_WIDTH
DB 5
DB SocketID
DB ChannelID
DB ALL_DIMMS
DB MinRdDataeyeWidth
DB MinWrDataeyeWidth
ENDM
MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
DB PSO_MEMORY_POWER_POLICY
DB 4
DB ANY_SOCKET
DB ANY_CHANNEL
DB ALL_DIMMS
DB PowerPolicy
ENDM
MOTHER_BOARD_LAYERS MACRO Layers:REQ
DB PSO_MOTHER_BOARD_LAYERS
DB 1
DB Layers
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
; *****************************************************************************************
; *
; * TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************
; Configuration sub-descriptors
CONFIG_GENERAL EQU 0
CONFIG_SPEEDLIMIT EQU 1
CONFIG_RC2IBT EQU 2
CONFIG_DONT_CARE EQU 3
Config_Type TEXTEQU <DWORD>
;
; Configuration Macros
;
TBLDRV_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
DB PSO_TBLDRV_CONFIG
DB 9
DB CONFIG_GENERAL
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
ENDM
TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ, NumOfLRDimm:REQ
DB PSO_TBLDRV_CONFIG
DB 7
DB CONFIG_SPEEDLIMIT
DB DimmPerCH
DB Dimms
DB NumOfSR
DB NumOfDR
DB NumOfQR
DB NumOfLRDimm
ENDM
TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE MACRO DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
DB PSO_TBLDRV_CONFIG
DB 10
DB CONFIG_RC2IBT
DB DimmPerCH
DB DimmVolt
DD Frequency
DW DimmConfig
DB NumOfReg
ENDM
;
; Overriding Macros
;
TBLDRV_CONFIG_ENTRY_SPEEDLIMIT MACRO SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
DB PSO_TBLDRV_SPEEDLIMIT
DB 6
DW SpeedLimit1_5
DW SpeedLimit1_35
DW SpeedLimit1_25
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTNOM MACRO TgtCS:REQ, RttNom:REQ
DB PSO_TBLDRV_ODT_RTTNOM
DB 2
DB TgtCS
DB RttNom
ENDM
TBLDRV_CONFIG_ENTRY_ODT_RTTWR MACRO TgtCS:REQ, RttWr:REQ
DB PSO_TBLDRV_ODT_RTTWR
DB 2
DB TgtCS
DB RttWr
ENDM
TBLDRV_CONFIG_ENTRY_ODTPATTERN MACRO RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
DB PSO_TBLDRV_ODTPATTERN
DB 16
DD RdODTCSHigh
DD RdODTCSLow
DD WrODTCSHigh
DD WrODTCSLow
ENDM
TBLDRV_CONFIG_ENTRY_ADDRTMG MACRO AddrTmg:REQ
DB PSO_TBLDRV_ADDRTMG
DB 4
DD AddrTmg
ENDM
TBLDRV_CONFIG_ENTRY_ODCCTRL MACRO OdcCtrl:REQ
DB PSO_TBLDRV_ODCCTRL
DB 4
DD OdcCtrl
ENDM
TBLDRV_CONFIG_ENTRY_SLOWACCMODE MACRO SlowAccMode:REQ
DB PSO_TBLDRV_SLOWACCMODE
DB 1
DB SlowAccMode
ENDM
TBLDRV_CONFIG_ENTRY_RC2_IBT MACRO TgtDimm:REQ, IBT:REQ
DB PSO_TBLDRV_RC2_IBT
DB 2
DB TgtDimm
DB IBT
ENDM
TBLDRV_OVERRIDE_MR0_CL MACRO RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_CL
DB 3
DB RegValOfTcl
DB MR0CL13
DB MR0CL0
ENDM
TBLDRV_OVERRIDE_MR0_WR MACRO RegValOfTwr:REQ, MR0WR:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_MR0_WR
DB 2
DB RegValOfTcl
DB MR0WR
ENDM
TBLDRV_OVERRIDE_RC10_OPSPEED MACRO Frequency:REQ, MR10OPSPEED:REQ
DB PSO_TBLDRV_CONFIG
DB 1
DB CONFIG_DONT_CARE
DB PSO_TBLDRV_RC10_OPSPEED
DB 5
DD Frequency
DB MR10OPSPEED
ENDM
TBLDRV_CONFIG_ENTRY_LRDMM_IBT MACRO F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
DB PSO_TBLDRV_LRDIMM_IBT
DB 4
DB F0RC8
DB F1RC0
DB F1RC1
DB F1RC2
ENDM
TBLDRV_CONFIG_ENTRY_2D_TRAINING MACRO Training2dMode:REQ
DB PSO_TBLDRV_2D_TRAINING
DB 1
DB Training2dMode
ENDM
;
; Macros for removing entries
;
INVALID_CONFIG_FLAG EQU 8000h
TBLDRV_INVALID_CONFIG MACRO
DB PSO_TBLDRV_INVALID_TYPE
DB 0
ENDM
; *****************************************************************************************
; *
; * END OF TABLE DRIVEN OVERRIDE MACROS
; *
; *****************************************************************************************

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src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc
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src/vendorcode/amd/agesa/f16kb/Legacy/amd.inc
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@ -1,462 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
;
; ****************************************************************************
; *
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AMD_GET_2D_DATA_EYE EQU 00020013h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', '!', 'A', 'G', 'E', 'S', 'A'>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (16) DUP (?) ; < 16 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

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src/vendorcode/amd/agesa/f16kb/Legacy/bridge32.inc
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@ -1,576 +0,0 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
;
; ****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

335
src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib32.asm
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@ -1,335 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 32bit
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.586p
.model flat
ASSUME FS:NOTHING
.code
public IdsDelay
IdsDelay PROC NEAR C USES EAX EDX
Local targetedx:dword, targeteax:dword
rdtsc
;set target time
add eax,1500000000
adc edx,0
mov targetedx,edx
mov targeteax,eax
rdtsc
;set "Si!=0" skip below loop
.while(1)
.if(si != 0)
jmp delay_exit
.endif
.if(edx > targetedx)
jmp delay_exit
.elseif (edx == targetedx)
.if(eax > targeteax)
jmp delay_exit
.endif
.endif
rdtsc
.endw
delay_exit:
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC NEAR C filecode:dword
local tmpebx:dword,tmpedx:dword
pushad
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, filecode
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov ebx,0dead0000h
mov edx,filecode
ror edx,16
mov bx,dx
mov dx,0
;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num
mov tmpebx,ebx
mov tmpedx,edx
xor eax,eax
mov cl,6
.while((cl != 0) && (si == 0))
.if(cl <= 2)
shld eax,edx,8
shl edx,8
.else
shld eax,ebx,8
shl ebx,8
.endif
out 80h,eax
call IdsDelay
dec cl
.if(cl == 0)
mov cl,6
mov ebx,tmpebx
mov edx,tmpedx
.endif
.endw
popad
xor eax,eax
ret
IdsErrorStop endp
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
IDS_STOP_HERE MACRO
@@:
jmp short @b
ENDM
;======================================================================
; IdsExceptionHandler: Simply performs a jmp $ and IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC _IdsExceptionHandler
PUBLIC _SizeIdtDescriptor
PUBLIC _SizeTotalIdtDescriptors
; Size of each exception MUST be the same
Exception00:
push eax
mov al, 00h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception01:
push eax
mov al, 01h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception02:
push eax
mov al, 02h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception03:
push eax
mov al, 03h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception04:
push eax
mov al, 04h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception05:
push eax
mov al, 05h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception06:
push eax
mov al, 06h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception07:
push eax
mov al, 07h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception08:
push eax
mov al, 08h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception09:
push eax
mov al, 09h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception10:
push eax
mov al, 10h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception11:
push eax
mov al, 11h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception12:
push eax
mov al, 12h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception13:
push eax
mov al, 13h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception14:
push eax
mov al, 14h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception15:
push eax
mov al, 15h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception16:
push eax
mov al, 16h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception17:
push eax
mov al, 17h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception18:
push eax
mov al, 18h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception19:
push eax
mov al, 19h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception20:
push eax
mov al, 20h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception21:
push eax
mov al, 21h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception22:
push eax
mov al, 22h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception23:
push eax
mov al, 23h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception24:
push eax
mov al, 24h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception25:
push eax
mov al, 25h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception26:
push eax
mov al, 26
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception27:
push eax
mov al, 27h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception28:
push eax
mov al, 28h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception29:
push eax
mov al, 29h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception30:
push eax
mov al, 30h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception31:
push eax
mov al, 31h
jmp near ptr CommonHandler
CommonHandler:
out 80h, al
pop eax
IDS_STOP_HERE
iretd
_IdsExceptionHandler dq offset Exception00
_SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
END

342
src/vendorcode/amd/agesa/f16kb/Proc/IDS/Control/IdsLib64.asm
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@ -1,342 +0,0 @@
;/**
; * @file
; *
; * Ids Assembly library 64bit
; *
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: IDS
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.code
IdsDelay PROC
push rax
push rdx
push rbx
xor rax,rax
xor rdx,rdx
rdtsc
;set target time
add eax,1500000000
adc edx,0
shl rdx,32
add rdx,rax
mov rbx,rdx
;rbx store the target
;set "Si!=0" skip below loop
__loop:
cmp si,0
jnz __loopexit
rdtsc
shl rdx,32
add rdx,rax
cmp rdx,rbx
jae __loopexit
jmp __loop
__loopexit:
pop rbx
pop rdx
pop rax
ret
IdsDelay ENDP
;/*++
;
;Routine Description:
;
; IdsErrorStop -- Function for Assert
;
;Arguments:
; Filecode
;
;Returns:
;
; None
;
;--*/
public IdsErrorStop
IdsErrorStop PROC
;As x64 calling convention RCX is used as input parameters
push rcx
push rbx
push si
push dx
push rbx
mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop
; send debug port 1st, then fire SimNow breakpoint
mov ax, 0deadh
out 0e0h, ax
mov eax, ecx
out 84h, eax
mov eax, 0BACCD00Bh ; Backdoor in SimNow
mov ebx, 2 ; Select breakpoint feature
cpuid
mov rax,0dead00000000h
or rcx,rax
;rcx= 0dead__FILECODE
shl rcx,16
;rcx= 0dead__FILECODE__0000
mov rbx,rcx
xor rax,rax
mov dl,6
IdsErrorStopLoop:
cmp dl,0
jz IdsErrorStopExit
cmp si,0
jnz IdsErrorStopExit
shld rax,rcx,8
shl rcx,8
out 80h,eax
call IdsDelay
dec dl
cmp dl,0
jnz _nextloop
mov dl,6
mov rcx,rbx
_nextloop:
jmp IdsErrorStopLoop
IdsErrorStopExit:
pop rbx
pop dx
pop si
pop rbx
pop rcx
xor rax,rax
ret
IdsErrorStop endp
;/*---------------------------------------------------------------------------------------*/
;/**
; * Stop CPU
; *
; *
; *
; */
IDS_STOP_HERE MACRO
@@:
jmp short @b
ENDM
;======================================================================
; IdsExceptionHandler: Simply performs a jmp $ and IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC IdsExceptionHandler
PUBLIC SizeIdtDescriptor
PUBLIC SizeTotalIdtDescriptors
; Size of each exception MUST be the same
Exception00:
push rax
mov al, 00h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception01:
push rax
mov al, 01h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception02:
push rax
mov al, 02h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception03:
push rax
mov al, 03h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception04:
push rax
mov al, 04h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception05:
push rax
mov al, 05h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception06:
push rax
mov al, 06h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception07:
push rax
mov al, 07h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception08:
push rax
mov al, 08h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception09:
push rax
mov al, 09h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception10:
push rax
mov al, 10h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception11:
push rax
mov al, 11h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception12:
push rax
mov al, 12h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception13:
push rax
mov al, 13h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception14:
push rax
mov al, 14h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception15:
push rax
mov al, 15h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception16:
push rax
mov al, 16h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception17:
push rax
mov al, 17h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception18:
push rax
mov al, 18h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception19:
push rax
mov al, 19h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception20:
push rax
mov al, 20h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception21:
push rax
mov al, 21h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception22:
push rax
mov al, 22h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception23:
push rax
mov al, 23h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception24:
push rax
mov al, 24h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception25:
push rax
mov al, 25h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception26:
push rax
mov al, 26
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception27:
push rax
mov al, 27h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception28:
push rax
mov al, 28h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception29:
push rax
mov al, 29h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception30:
push rax
mov al, 30h
jmp near ptr CommonHandler
; Size of each exception MUST be the same
Exception31:
push rax
mov al, 31h
jmp near ptr CommonHandler
CommonHandler:
out 80h, al
pop rax
IDS_STOP_HERE
iretq
IdsExceptionHandler dq offset Exception00
SizeIdtDescriptor dd (offset Exception01 - offset Exception00)
SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00)
END

496
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mu.asm
View File

@ -1,496 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; $Workfile:: mu.asm $ $Revision:: 841#$ $Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
; Description: Main memory controller system configuration for AGESA
;
;
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
;============================================================================
.XLIST
.LIST
.686p
.MODEL FLAT
.CODE
ASSUME FS: NOTHING
; Define the calling convention used for the C library modules
;@attention - This should be in a central include file
CALLCONV EQU NEAR C
;===============================================================================
;memUOutPort:
;
; Do a 32 Bit IO Out operation using edx.
; NOTE: This function will be obsolete in the future.
;
; In: Port - port number
; Value - value to be written
;
; Out:
;
; All registers preserved.
;===============================================================================
MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
pushad
mov edx,Port
mov eax,Value
out dx,al
popad
ret
MemUOutPort ENDP
;----------------------------------------------------------------------------
; _SFENCE();
;
_SFENCE macro
db 0Fh,0AEh,0F8h
endm
;----------------------------------------------------------------------------
; _MFENCE();
;
_MFENCE macro
db 0Fh,0AEh,0F0h
endm
;----------------------------------------------------------------------------
; _EXECFENCE();
;
_EXECFENCE macro
out 0EDh,al ;prevent speculative execution of following instructions
endm
;===============================================================================
;MemUWriteCachelines:
; Write a test pattern to DRAM
;
; In: Pattern - pointer to the write pattern
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
pushad
push ds
mov eax,Address
push ss
pop ds
xor edx,edx
mov edx, DWORD PTR Pattern
mov esi,edx
mov edx,16
_EXECFENCE
xor ecx, ecx
mov cx,ClCount
shl ecx,2
@@:
db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
add eax,edx
add esi,edx
loop @B
pop ds
popad
ret
MemUWriteCachelines ENDP
;===============================================================================
;MemUReadCachelines:
;
; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
;pattern is a stress pattern which exercises both ISI and crosstalk. The number
;of cache lines to fill is dependent on DCT width mode and burstlength.
;
; In: Buffer - pointer to a buffer where read data will be stored
; Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL Count:BYTE
pushad
; First, issue continuous dummy reads to fill up the cache
mov eax,Address
.if (ClCount > 18)
mov cx,ClCount
shr cx,4
mov Count,cl
.while (Count != 0)
push eax
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
pop eax
add eax,(16*64) ;Next 16CL
dec Count
.endw
.else
mov edi,eax
add edi,128 ;bias value (to account for signed displacement)
;clflush opcode=0F AE /7
mov esi,edi
mov ebx,esi
mov ecx,esi
mov edx,esi
add edi,4*64 ;TestAddr+4 cache lines
add ebx,8*64 ;TestAddr+8 cache lines
add ecx,12*64 ;TestAddr+12 cache lines
add edx,16*64 ;TestAddr+16 cache lines
sub edx,128
.if(ClCount == 1)
_MFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
.elseif(ClCount == 3)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
.elseif(ClCount == 6)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
.elseif(ClCount == 9)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
.elseif(ClCount == 18)
_EXECFENCE
mov eax,fs:[esi-128] ;TestAddr
_MFENCE
mov eax,fs:[esi-64] ;TestAddr+1 cache line
_MFENCE
mov eax,fs:[esi] ;TestAddr+2 cache lines
_MFENCE
mov eax,fs:[esi+64] ;TestAddr+3 cache lines
_MFENCE
mov eax,fs:[edi-128] ;TestAddr+4 cache lines
_MFENCE
mov eax,fs:[edi-64] ;TestAddr+5 cache lines
_MFENCE
mov eax,fs:[edi] ;TestAddr+6 cache lines
_MFENCE
mov eax,fs:[edi+64] ;TestAddr+7 cache lines
_MFENCE
mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
_MFENCE
mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
_MFENCE
mov eax,fs:[ebx] ;TestAddr+10 cache lines
_MFENCE
mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
_MFENCE
mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
_MFENCE
mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
_MFENCE
mov eax,fs:[ecx] ;TestAddr+14 cache lines
_MFENCE
mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
_MFENCE
mov eax,fs:[edx] ;TestAddr+16 cache lines
_MFENCE
mov eax,fs:[edx+64] ;TestAddr+17 cache lines
_MFENCE
.endif
.endif
_MFENCE
; Then, copy data to buffer
mov esi,Address
xor edx,edx
mov edx,DWORD PTR Buffer
mov edi,edx
xor ecx, ecx
mov cx,ClCount
shl ecx,6
@@:
mov al,fs:[esi]
mov ss:[edi],al
inc esi
inc edi
loop @B
popad
ret
MemUReadCachelines ENDP
;===============================================================================
;MemUDummyCLRead:
;
; Perform a single cache line read from a given physical address.
;
; In: Address - Physical address to be read
; ClCount - number of cachelines to be read
; Out:
;
;All registers preserved.
;===============================================================================
MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
_SFENCE
pushad
mov eax,Address
mov dl,fs:[eax]
popad
ret
MemUDummyCLRead ENDP
;===============================================================================
;MemUFlushPattern:
;
; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
;to ensure cache miss on the next read training.
;
; In: Address - Physical address to be flushed
; ClCount - number of cachelines to be flushed
; Out:
;
;All registers preserved.
;===============================================================================
MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
pushad
mov edi,Address
movzx ecx,ClCount
@@:
_MFENCE ; Force strong ordering of clflush
db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
_MFENCE
add edi,64
loop @B
popad
ret
MemUFlushPattern ENDP
;===============================================================================
;MemUGetWrLvNblErr:
; Read ClCount number of cachelines then return the bitmap that indicates
; the write leveling result of each byte lane.
;
; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
; Address - Physical address to be sampled
; ClCount - number of cachelines to be read
;
; OUT: ErrBitmap - WL result
;
;All registers preserved
;===============================================================================
MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
LOCAL ZeroCount[32]:WORD
pushad
mov esi,Address
_EXECFENCE
;Cache fill
movzx ecx,ClCount
@@:
mov eax,fs:[esi]
add esi,64
loop @B
_MFENCE
; Then, count the number of 0's
;push es
;push ss
;pop es
lea edi,ZeroCount
mov cx,SIZEOF ZeroCount
mov al,0
rep stosb
;pop es
mov esi,Address
lea edi,ZeroCount
mov cx,ClCount
shl cx,6
.while(cx > 0)
mov al,fs:[esi]
test al,00Fh ;check lower nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
test al,0F0h ;check upper nibble
.if(ZERO?)
inc WORD PTR [edi]
.endif
add edi,2
inc esi
dec cx
test cx,07h
.if(ZERO?)
sub edi,(16*2)
sub cx,8
add esi,8
.endif
.endw
; Then, average and compress data to error bits
lea esi,ZeroCount
mov dx,ClCount
shl dx,1
xor eax,eax
xor ecx,ecx
mov cl,0
.while(cl<16)
.if(WORD PTR [esi] < dx)
bts eax,ecx
.endif
add esi,2
inc cl
.endw
xor edx,edx
mov dx,WORD PTR ErrBitmap
mov [edx], ax
popad
ret
MemUGetWrLvNblErr ENDP
;===============================================================================
;AlignPointerTo16Byte:
; Modifies BufferPtr to be 16 byte aligned
;
; In: BufferPtrPtr - Pointer to buffer pointer
; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
;
;All registers preserved.
;===============================================================================
AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
push edx
push eax
mov edx, BufferPtrPtr
mov eax, [edx]
add eax, 16
and ax, 0FFF0h
mov [edx], eax
pop eax
pop edx
ret
AlignPointerTo16Byte ENDP
;===============================================================================
;MemUMFenceInstr:
; Serialize instruction
;
; In:
; Out:
;
;All registers preserved.
;===============================================================================
MemUMFenceInstr PROC CALLCONV PUBLIC
_MFENCE
ret
MemUMFenceInstr ENDP
END