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Update memory settings for thelio-b1

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Jeremy Soller 2019-05-06 11:47:23 -06:00
parent 51802ead2d
commit b99d0bfa32
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GPG Key ID: E988B49EE78A7FB1
1 changed files with 6 additions and 6 deletions
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src/mainboard/system76/thelio-b1/romstage.c
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@ -55,14 +55,14 @@ static const struct cnl_mb_cfg memcfg = {
* ohms of the three rcomp resistors attached to the DDR_COMP_0, * ohms of the three rcomp resistors attached to the DDR_COMP_0,
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
*/ */
// These are the recommended settings for CFL-S // These are the recommended settings for CFL-S DDR4 UDIMM (See PDG)
.rcomp_resistor = { 121, 75, 100 }, .rcomp_resistor = { 121, 75, 100 },
/* /*
* Rcomp target values. These will typically be the following * Rcomp target values. These will typically be the following
* values for Cannon Lake : { 80, 40, 40, 40, 30 } * values for Cannon Lake : { 80, 40, 40, 40, 30 }
*/ */
// These are the recommended settings for CFL-S // These are the recommended settings for CFL-S DDR4 UDIMM (See PDG)
.rcomp_targets = { 60, 26, 20, 20, 26 }, .rcomp_targets = { 60, 26, 20, 20, 26 },
/* /*
@ -70,7 +70,7 @@ static const struct cnl_mb_cfg memcfg = {
* Set to 1 for an interleaved design, * Set to 1 for an interleaved design,
* set to 0 for non-interleaved design. * set to 0 for non-interleaved design.
*/ */
// TODO: Find correct settings // These are the recommended settings for CFL-S DDR4 UDIMM (See PDG)
.dq_pins_interleaved = 1, .dq_pins_interleaved = 1,
/* /*
@ -79,12 +79,12 @@ static const struct cnl_mb_cfg memcfg = {
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
*/ */
// These are the recommended settings for DDR4 // These are the recommended settings for CFL-S DDR4 UDIMM (See PDG)
.vref_ca_config = 2, .vref_ca_config = 2,
/* Early Command Training Enabled */ /* Early Command Training Enabled */
// TODO: Find correct settings // TODO: Find correct settings, default appears to be 1
.ect = 0, .ect = 1,
}; };
void mainboard_memory_init_params(FSPM_UPD *memupd) { void mainboard_memory_init_params(FSPM_UPD *memupd) {