nb/intel/x4x: Clean up cosmetics of raminit tables
Consistently use commas after the last element of arrays, and also align columns of values and comments. Remove `MHz` units from DDR speed values to avoid confusion, as the memory's actual clock speed is half of these. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
committed by
Patrick Georgi
Patrick Georgi
parent
32f9bcaa91
commit
b99d592752
@@ -33,7 +33,7 @@ const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES] = {
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{9, 1, 0, 0, 1, 0},
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{6, 4, 0, 0, 1, 0},
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{6, 2, 0, 0, 1, 0},
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{5, 4, 0, 0, 1, 0}
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{5, 4, 0, 0, 1, 0},
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};
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const struct dll_setting default_ddr2_800_ctrl[7] = {
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@@ -66,7 +66,7 @@ const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES] = {
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{10, 0, 0, 0, 1, 0},
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{8, 1, 0, 0, 1, 0},
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{7, 5, 0, 0, 1, 0},
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{6, 2, 0, 0, 1, 0}
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{6, 2, 0, 0, 1, 0},
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};
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const struct dll_setting default_ddr3_800_ctrl[2][7] = {
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@@ -78,7 +78,8 @@ const struct dll_setting default_ddr3_800_ctrl[2][7] = {
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{6, 1, 0, 0, 0, 0},
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{8, 4, 0, 0, 0, 0},
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{10, 0, 0, 0, 0, 0},
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{10, 0, 0, 0, 0, 0}, },
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{10, 0, 0, 0, 0, 0},
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},
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{ /* 2N */
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{2, 2, 1, 1, 0, 0},
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{2, 4, 1, 1, 0, 0},
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@@ -86,7 +87,8 @@ const struct dll_setting default_ddr3_800_ctrl[2][7] = {
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{3, 2, 1, 1, 0, 0},
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{2, 4, 1, 1, 0, 0},
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{3, 6, 0, 0, 0, 0},
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{3, 6, 0, 0, 0, 0}, }
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{3, 6, 0, 0, 0, 0},
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},
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};
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const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = {
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@@ -98,7 +100,8 @@ const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = {
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{4, 3, 0, 0, 1, 0},
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{5, 2, 0, 0, 1, 0},
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{6, 1, 0, 0, 1, 0},
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{6, 4, 0, 0, 1, 0}, },
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{6, 4, 0, 0, 1, 0},
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},
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{ /* 2N */
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{5, 6, 0, 0, 0, 0},
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{8, 0, 0, 0, 0, 0},
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@@ -107,7 +110,8 @@ const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = {
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{11, 3, 1, 0, 0, 0},
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{12, 1, 1, 0, 0, 0},
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{0, 1, 1, 1, 1, 0},
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{0, 3, 1, 1, 1, 0}, }
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{0, 3, 1, 1, 1, 0},
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},
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};
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const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = {
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@@ -119,7 +123,8 @@ const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = {
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{9, 5, 0, 0, 1, 0},
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{10, 2, 0, 0, 1, 0},
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{10, 6, 1, 0, 1, 0},
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{11, 4, 1, 0, 1, 0} },
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{11, 4, 1, 0, 1, 0},
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},
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{ /* 2N */
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{11, 0, 1, 0, 0, 0},
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{0, 3, 1, 1, 1, 0},
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@@ -128,7 +133,8 @@ const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = {
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{3, 5, 0, 0, 1, 0},
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{4, 2, 0, 0, 1, 0},
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{4, 6, 0, 0, 1, 0},
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{5, 4, 0, 0, 1, 0}, }
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{5, 4, 0, 0, 1, 0},
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},
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};
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const struct dll_setting default_ddr3_1067_ctrl[2][7] = {
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@@ -139,7 +145,8 @@ const struct dll_setting default_ddr3_1067_ctrl[2][7] = {
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{4, 4, 0, 0, 0, 0},
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{7, 6, 0, 0, 0, 0},
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{9, 2, 1, 0, 0, 0},
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{9, 2, 1, 0, 0, 0}, },
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{9, 2, 1, 0, 0, 0},
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},
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{ /* 2N */
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{1, 5, 1, 1, 0, 0},
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{0, 6, 1, 1, 0, 0},
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@@ -147,7 +154,8 @@ const struct dll_setting default_ddr3_1067_ctrl[2][7] = {
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{2, 6, 1, 1, 0, 0},
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{0, 6, 1, 1, 0, 0},
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{2, 2, 1, 1, 0, 0},
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{2, 2, 1, 1, 0, 0}, }
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{2, 2, 1, 1, 0, 0},
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},
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};
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const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = {
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@@ -159,7 +167,8 @@ const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = {
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{8, 6, 0, 0, 1, 0},
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{9, 6, 1, 0, 1, 0},
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{10, 6, 1, 0, 1, 0},
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{0, 1, 1, 1, 0, 1}, },
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{0, 1, 1, 1, 0, 1},
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},
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{ /* 2N */
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{6, 4, 0, 0, 0, 0},
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{9, 1, 1, 0, 0, 0},
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@@ -169,7 +178,7 @@ const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = {
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{2, 5, 1, 1, 1, 0},
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{3, 5, 0, 0, 1, 0},
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{4, 1, 0, 0, 1, 0},
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}
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},
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};
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const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = {
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@@ -181,7 +190,8 @@ const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = {
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{2, 0, 1, 1, 0, 1},
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{2, 5, 1, 1, 0, 1},
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{3, 2, 0, 0, 0, 1},
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{4, 1, 0, 0, 0, 1}, },
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{4, 1, 0, 0, 0, 1},
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},
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{ /* 2N */
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{10, 5, 1, 0, 0, 0},
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{2, 3, 1, 1, 1, 0},
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@@ -191,7 +201,7 @@ const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = {
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{6, 5, 0, 0, 1, 0},
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{7, 2, 0, 0, 1, 0},
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{8, 1, 0, 0, 1, 0},
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}
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},
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};
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const struct dll_setting default_ddr3_1333_ctrl[2][7] = {
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@@ -202,7 +212,8 @@ const struct dll_setting default_ddr3_1333_ctrl[2][7] = {
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{0, 0, 1, 1, 0, 0},
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{9, 0, 1, 0, 0, 0},
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{10, 4, 1, 0, 0, 0},
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{10, 4, 1, 0, 0, 0}, },
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{10, 4, 1, 0, 0, 0},
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},
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{ /* 2N */
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{1, 6, 1, 1, 0, 0},
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{2, 2, 1, 1, 0, 0},
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@@ -210,7 +221,8 @@ const struct dll_setting default_ddr3_1333_ctrl[2][7] = {
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{3, 1, 1, 1, 0, 0},
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{2, 2, 1, 1, 0, 0},
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{4, 5, 0, 0, 0, 0},
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{4, 5, 0, 0, 0, 0}, }
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{4, 5, 0, 0, 0, 0},
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},
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};
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const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = {
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@@ -222,7 +234,8 @@ const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = {
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{8, 6, 0, 0, 1, 0},
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{9, 5, 1, 0, 1, 0},
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{10, 6, 1, 0, 1, 0},
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{0, 1, 1, 1, 0, 1}, },
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{0, 1, 1, 1, 0, 1},
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},
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{ /* 2N */
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{10, 4, 0, 0, 0, 0},
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{0, 3, 1, 1, 1, 0},
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@@ -231,7 +244,8 @@ const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = {
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{6, 1, 0, 0, 1, 0},
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{7, 4, 0, 0, 1, 0},
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{9, 2, 0, 0, 1, 0},
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{9, 6, 0, 0, 1, 0}, }
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{9, 6, 0, 0, 1, 0},
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},
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};
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const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = {
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@@ -243,7 +257,8 @@ const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = {
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{2, 0, 1, 1, 0, 1},
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{2, 5, 1, 1, 0, 1},
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{3, 2, 0, 0, 0, 1},
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{4, 1, 0, 0, 0, 1}, },
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{4, 1, 0, 0, 0, 1},
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},
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{ /* 2N */
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{1, 3, 1, 1, 1, 0},
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{5, 6, 0, 0, 1, 0},
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@@ -252,7 +267,8 @@ const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = {
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{11, 1, 0, 0, 1, 0},
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{12, 3, 1, 0, 1, 0},
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{13, 6, 1, 0, 1, 0},
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{0, 3, 1, 1, 0, 1}, }
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{0, 3, 1, 1, 0, 1},
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},
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};
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const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
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@@ -274,35 +290,38 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */
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{0x81, 0x00, 0x81, 0x00}, /* 16S_16S */
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};
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const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
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const u8 post_jedec_tab[3][4][2] = { /* [FSB][DDR freq][17:13 or 12:8] */
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{ /* FSB DDR */
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{{0x3, 0x5}, /* 800 667 */
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{0x3, 0x5}, /* 800 667 */
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{0x3, 0x4}, /* 800 800 */
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},
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{{0x4, 0x8}, /* 1067 667 */
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{
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{0x4, 0x8}, /* 1067 667 */
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{0x4, 0x6}, /* 1067 800 */
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{0x3, 0x5}, /* 1067 1066 */
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},
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{{0x5, 0x9}, /* 1333 667 */
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{
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{0x5, 0x9}, /* 1333 667 */
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{0x4, 0x7}, /* 1333 800 */
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{0x4, 0x7}, /* 1333 1066 */
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{0x4, 0x7} /* 1333 1333 */
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{0x4, 0x7}, /* 1333 1333 */
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},
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};
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const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
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/* 115h[15:0] 117h[23:0] */
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{ /* 1N mode */
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{ /* DDR3 800MHz */
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{ /* DDR3 800 */
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{0x0189, 0x000aaa}, /* CAS = 5 */
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{0x0189, 0x101aaa}, /* CAS = 6 */
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},
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{ /* DDR3 1067MHz */
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{ /* DDR3 1067 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0089, 0x000bbb}, /* CAS = 6 */
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{0x0099, 0x101bbb}, /* CAS = 7 */
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{0x0099, 0x202bbb} /* CAS = 8 */
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},{ /* DDR3 1333 */
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{0x0099, 0x202bbb}, /* CAS = 8 */
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},
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{ /* DDR3 1333 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0000, 0x000000}, /* CAS = 6 - Not supported */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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@@ -312,18 +331,17 @@ const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
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},
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},
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{ /* 2N mode */
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{ /* DDR3 800MHz */
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{ /* DDR3 800 */
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{0x0189, 0x000aaa}, /* CAS = 5 */
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{0x0189, 0x101aaa}, /* CAS = 6 */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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{0x0000, 0x000000} /* CAS = 8 - Not supported */
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},
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{ /* DDR3 1067 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0089, 0x000bbb}, /* CAS = 6 */
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{0x0099, 0x101bbb}, /* CAS = 7 */
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{0x0099, 0x202bbb} /* CAS = 8 */
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},{ /* DDR3 1333MHz */
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{0x0099, 0x202bbb}, /* CAS = 8 */
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},
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{ /* DDR3 1333 */
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{0x0000, 0x000000}, /* CAS = 5 - Not supported */
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{0x0000, 0x000000}, /* CAS = 6 - Not supported */
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{0x0000, 0x000000}, /* CAS = 7 - Not supported */
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@@ -331,42 +349,47 @@ const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
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{0x019a, 0x1088dc}, /* CAS = 9 */
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{0x019a, 0x2098dc}, /* CAS = 10 */
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},
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}
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},
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};
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const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */
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/* DDR3 800MHz */
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{0x78, /* CAS = 5 */
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0x89}, /* CAS = 6 */
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/* DDR3 1066 */
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{0x00, /* CAS = 5 - Not supported */
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{ /* DDR3 800 */
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0x78, /* CAS = 5 */
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0x89, /* CAS = 6 */
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},
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{ /* DDR3 1066 */
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0x00, /* CAS = 5 - Not supported */
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0xff, /* CAS = 6 */
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0x8a, /* CAS = 7 */
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0x9a}, /* CAS = 8 */
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/* DDR3 1333 */
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{0x00, /* CAS = 5 - Not supported */
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0x9a, /* CAS = 8 */
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},
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{ /* DDR3 1333 */
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0x00, /* CAS = 5 - Not supported */
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0x00, /* CAS = 6 - Not supported */
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0xff, /* CAS = 7 - Not supported */
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0xff, /* CAS = 8 */
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0xff, /* CAS = 9 */
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0xff}, /* CAS = 10 */
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0xff, /* CAS = 10 */
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},
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};
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const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */
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/* DDR3 800MHz */
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{0x9bbb, /* CAS = 5 */
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0x8bbb}, /* CAS = 6 */
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/* DDR3 1066MHz */
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{0x0000, /* CAS = 5 - Not supported */
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{ /* DDR3 800 */
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0x9bbb, /* CAS = 5 */
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0x8bbb, /* CAS = 6 */
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},
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{ /* DDR3 1066 */
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0x0000, /* CAS = 5 - Not supported */
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0x9baa, /* CAS = 6 */
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0x8caa, /* CAS = 7 */
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0x7daa}, /* CAS = 8 */
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/* DDR3 1333MHz */
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{0x0000, /* CAS = 5 - Not supported */
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0x7daa, /* CAS = 8 */
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},
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{ /* DDR3 1333 */
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0x0000, /* CAS = 5 - Not supported */
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0x0000, /* CAS = 6 - Not supported */
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0x0000, /* CAS = 7 - Not supported */
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0xaecb, /* CAS = 8 */
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0x9fcb, /* CAS = 9 */
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0x8fcb}, /* CAS = 10 */
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0x8fcb, /* CAS = 10 */
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},
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};
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