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vc/amd/agesa/f15tn: Drop dead code

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This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I9ceb37186e3622f2eac37393fa7ac5ced8efadf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43258
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-08 00:26:55 +02:00
parent 82ab9ca72c
commit b9bdcaecc1
4 changed files with 0 additions and 156 deletions
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37
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
View File

@ -200,44 +200,7 @@ GnbLibFindPciCapability (
} }
return CapabilityPtr; return CapabilityPtr;
} }
/*----------------------------------------------------------------------------------------*/
/*
* Find PCIe extended capability pointer
*
*
*
* @param[in] Address PCI address (as described in PCI_ADDR)
* @param[in] ExtendedCapabilityId Extended PCIe capability ID
* @param[in] StdHeader Standard configuration header
* @retval Register address of extended capability pointer
*
*/
#if 0 /* Not used */
UINT16
GnbLibFindPcieExtendedCapability (
IN UINT32 Address,
IN UINT16 ExtendedCapabilityId,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 CapabilityPtr;
UINT32 ExtendedCapabilityIdBlock;
if (GnbLibPciIsPcieDevice (Address, StdHeader)) {
GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) {
do {
CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff);
if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) {
return CapabilityPtr;
}
GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
} while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0);
}
}
return 0;
}
#endif
/*----------------------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------------------*/
/* /*
* Scan range of device on PCI bus. * Scan range of device on PCI bus.

34
src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c
View File

@ -77,27 +77,6 @@ IdsAgesaTestPoint (
LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PORT, &TestPoint, StdHeader); LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PORT, &TestPoint, StdHeader);
} }
/**
*
* HDT out Function for Assert.
*
* fire a HDTOUT Command of assert to let hdtout script do corresponding things.
*
* @param[in,out] FileCode FileCode of the line
*
**/
#if 0
VOID
AmdIdsDebugPrintAssert (
IN UINT32 FileCode
)
{
//TODO:if (AmdIdsHdtOutSupport ()) {
// IdsOutPort (HDTOUT_ASSERT, FileCode, 0);
//}
}
#endif
/** /**
* IDS Backend Function for ASSERT * IDS Backend Function for ASSERT
* *
@ -123,7 +102,6 @@ IdsAssert (
IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line); IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line);
IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL); IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL);
IDS_HDT_CONSOLE_ASSERT (FileCode); IDS_HDT_CONSOLE_ASSERT (FileCode);
//IdsErrorStop (FileCode);
return TRUE; return TRUE;
} }
@ -140,18 +118,6 @@ IdsMemTimeOut (
IN OUT VOID *DataPtr IN OUT VOID *DataPtr
) )
{ {
//TODO: UINTN i;
//
// IDS_DEBUG_PRINT **DebugPrintList;
//
// GetDebugPrintList (&DebugPrintList);
//
// for (i = 0; DebugPrintList[i] != NULL; i++) {
// if (DebugPrintList[i]->support ()) {
// // Turn timeout off if any Debug service is on
// *((UINT8 *)DataPtr) = (UINT8)0;
// }
// }
} }
/** /**

32
src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c
View File

@ -105,38 +105,6 @@ AmdGetIdsNvTable (
return status; return status;
} }
/**
*
* Get IDS Override Image Base Address
*
* @param[in,out] IdsImageBase The Base Address of IDS Override Image.
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of NV Table.
* @retval AGESA_ERROR Fail to get the pointer of NV Table.
*
**/
#if 0
AGESA_STATUS
AmdGetIdsImagebase (
IN OUT UINT64 *IdsImageBase,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
IDS_CONTROL_STRUCT *IdsCtrlPtr;
LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status == AGESA_SUCCESS) {
IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr;
*IdsImageBase = IdsCtrlPtr->IdsImageBase;
}
return status;
}
#endif
/** /**
* *
* Read IDS NV value in NV table. * Read IDS NV value in NV table.

53
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c
View File

@ -80,13 +80,6 @@ RDATA_GROUP (G3_DXE)
* *
*---------------------------------------------------------------------------- *----------------------------------------------------------------------------
*/ */
#if 0
UINT32
STATIC
MemNGetODTDelaysTN (
IN OUT MEM_NB_BLOCK *NBPtr
);
#endif
/*---------------------------------------------------------------------------- /*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS * EXPORTED FUNCTIONS
@ -273,49 +266,3 @@ MemNSetOtherTimingTN (
IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd ); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd );
IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO ); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO );
} }
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function gets the ODT delays
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
*/
#if 0
UINT32
STATIC
MemNGetODTDelaysTN (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
INT8 Ld;
UINT32 ODTDelays;
//
// The BIOS must additionally configure the ODT pattern
// and the ODT switching delays.
//
// Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
// -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
// -Value of 2, BL = 4 else assume BL=8.
// -Initialize ODTDelays based on BL value
// -WrOdtOnDuration [14:12] = BL / 2 + 1
// -WrOdtTrnOnDly [10:8] = 0
// -RdOdtOnDuration [6:4] = BL / 2 + 1
//
ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
// RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
// See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
if (Ld < 0) {
Ld = 0;
}
if (Ld > 7) {
Ld = 7;
}
ODTDelays += Ld;
return ODTDelays;
}
#endif