From b9ee6f351b4552f024edee3f1e1d72a4a09ec45a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 7 Mar 2022 17:03:27 +0100 Subject: [PATCH] mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLED Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel --- src/mainboard/amd/chausie/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index f3a84f31e9..7f37be2128 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -24,7 +24,7 @@ chip soc/amd/sabrina register "s0ix_enable" = "true" - register "pspp_policy" = "DXIO_PSPP_BALANCED" + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on device ref iommu on end