mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Michał Żygowski
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Patrick Georgi
Patrick Georgi
parent
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commit
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@ -71,6 +71,10 @@ The boards in this section are not real mainboards, but emulators.
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- [T4xx common](lenovo/t4xx_series.md)
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- [X2xx common](lenovo/x2xx_series.md)
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## Libretrend
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- [LT1000](libretrend/lt1000.md)
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### Nehalem series
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- [T410](lenovo/t410.md)
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Documentation/mainboard/libretrend/lt1000.md
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Documentation/mainboard/libretrend/lt1000.md
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# Libretrend LT1000
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This page describes how to run coreboot on the [Libretrend LT1000] (aka
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Librebox).
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## Required proprietary blobs
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To build a minimal working coreboot image some blobs are required (assuming
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only the BIOS region is being modified).
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```eval_rst
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+-----------------+---------------------------------+---------------------+
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| Binary file | Apply | Required / Optional |
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+=================+=================================+=====================+
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| FSP-M, FSP-S | Intel Firmware Support Package | Required |
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+-----------------+---------------------------------+---------------------+
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| microcode | CPU microcode | Required |
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+-----------------+---------------------------------+---------------------+
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```
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FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done
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automatically by coreboot build system and included into the image) from the
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*3rdparty/fsp* submodule.
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Microcode updates are automatically included into the coreboot image by build
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system from the *3rdparty/intel-microcode* submodule.
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The mainboard code also contains a VBT file (version 1.00, BDB version 2.09)
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which is automatically included into the image by coreboot build system.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. It is strongly advised to
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flash only the BIOS region if not having an external programmer, see known
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issues.
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### External programming
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The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
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This chip is located on the top middle side of the board near the CPU fan,
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between the DIMM slots and the M.2 disk. Use a clip (or solder the wires) to
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program the chip. Specifically, it's a Winbond W25Q64FV (3.3V) -
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[datasheet][W25Q64FV].
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## Known issues
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- Fastboot (MRC cache) is not working reliably (missing schematics for CPU to
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DIMM wiring).
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- Flashing ME region with already cleaned ME firmware may lead to platform not
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booting, flashing full ME firmware is needed to recover.
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- In order to have the USB device wake support from S3 state using the front
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USB 3.0 ports, one has to move the jumper on DUSB1_PWR_SET header (it will
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switch the power rails for the USB 3.0 ports).
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- There are 6 unknown GPIO pins on the board.
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## Untested
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Not all mainboard's peripherals and functions were tested because of lack of
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the cables or not being populated on the board case.
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- LVDS header
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- Onboard USB 2.0 and USB 3.0 headers
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- Speakers and mic header
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- SPDIF header
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- Audio header
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- PS/2 header
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- LPT header
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- CIR (infrared header)
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- COM2 port RS485 mode (RS232/RS485 mode is controlled via jumper)
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- SYS_FAN header
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## Working
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- USB
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- Ethernet
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- Integrated graphics (with libgfxinit) on VGA and HDMI ports
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- flashrom
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- PCIe
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- NVMe
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- WiFi and Bluetooth
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- SATA
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- Serial ports 1-6
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- SMBus
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- HDA (verbs not implemented yet, but works under GNU/Linux (4.15 tested))
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- Initialization with KBL FSP 2.0
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- SeaBIOS payload (version rel-1.13.0)
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- TPM2 ([custom module] connected to LPC DEBUG header)
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- Automatic fan control
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- Platform boots with cleaned ME (MFS partition must be left on SPI flash)
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## Technology
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The platform contains an LR-i7S65T1 baseboard (LR-i7S65T2 with two NICs not
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sold yet). More details on [baseboard site]. Unfortunately the board manual is
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not publicly available.
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Core i7-6500U |
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+------------------+--------------------------------------------------+
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| PCH | Skylake-U Premium |
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+------------------+--------------------------------------------------+
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| Super I/O | ITE IT8786E |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[Libretrend LT1000]: https://libretrend.com/specs/librebox/
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[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[baseboard site]: http://www.minicase.net/product_LR-i7S65T1.html
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[custom module]: https://shop.3mdeb.com/product/tpm2-module-for-librebox/
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