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src/southbridge: Code formating

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Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Elyes HAOUAS
2016-08-31 19:22:16 +02:00
committed by Martin Roth
parent 2e4d80687d
commit ba28e8d73b
130 changed files with 1484 additions and 1589 deletions
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4
src/southbridge/intel/ibexpeak/azalia.c
View File

@@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/ibexpeak/lpc.c
View File

@@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

2
src/southbridge/intel/ibexpeak/sata.c
View File

@@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0x28, reg32);
} else {
/* IDE */
/* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */

8
src/southbridge/intel/ibexpeak/smbus.h
View File

@@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
} while(status & 0x01);
} while (status & 0x01);
return 0;
}
@@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
} while(status & 0x01);
} while (status & 0x01);
return bytes_read;
}

54
src/southbridge/intel/ibexpeak/smihandler.c
View File

@@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
int slot, func;
unsigned int val;
unsigned char hdr;
int slot, func;
unsigned int val;
unsigned char hdr;
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
device_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
val = pci_read_config32(dev, PCI_VENDOR_ID);
if (val == 0xffffffff || val == 0x00000000 ||
val == 0x0000ffff || val == 0xffff0000)
continue;
if (val == 0xffffffff || val == 0x00000000 ||
val == 0x0000ffff || val == 0xffff0000)
continue;
/* Disable Bus Mastering for this one device */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Disable Bus Mastering for this one device */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
if (hdr == PCI_HEADER_TYPE_BRIDGE ||
hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
}
}
}
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
if (hdr == PCI_HEADER_TYPE_BRIDGE ||
hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
}
}
}
}
static void southbridge_gate_memory_reset_real(int offset,
@@ -849,7 +849,7 @@ void southbridge_smi_handler(void)
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}