mb/razer/blade_stealth_kbl: Add H3Q variant

The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U
variant, as originally committed, with the SKU number RZ09-01962, also
known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963
and RZ09-01964, known as the Mid 2017 model. This commit adds support
for the H3Q model. With respect to coreboot, there are few known
differences:

1. Only the H2U has TPM.
2. The USB ports are different.
3. The screen size (and therefore VBIOS Table) is different.
4. The hda_verb is very slightly different.
5. The gpio is different.

Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4
Signed-off-by: Reagan Bohan <xbjfk.github@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/razer/blade_stealth_kbl/Kconfig

@@ -1,16 +1,12 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_RAZER_BLADE_STEALTH_KBL
+config BOARD_RAZER_BLADE_STEALTH_KBL
-
+	bool
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
 	select SYSTEM_TYPE_LAPTOP
 	select BOARD_ROMSIZE_KB_8192
 	select SUPERIO_ITE_IT8528E
 	select SOC_INTEL_KABYLAKE
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
-	select MEMORY_MAPPED_TPM
-	select MAINBOARD_HAS_TPM2
 	select MAINBOARD_HAS_LIBGFXINIT
 	select HAVE_SPD_IN_CBFS
 	select DRIVERS_I2C_HID
@@ -18,6 +14,31 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select DRIVERS_GENERIC_CBFS_SERIAL
 
+config BOARD_RAZER_BLADE_H2U
+	select BOARD_RAZER_BLADE_STEALTH_KBL
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+
+config BOARD_RAZER_BLADE_H3Q
+	select BOARD_RAZER_BLADE_STEALTH_KBL
+
+if BOARD_RAZER_BLADE_STEALTH_KBL
+
+config VARIANT_DIR
+	default "h2u" if BOARD_RAZER_BLADE_H2U
+	default "h3q" if BOARD_RAZER_BLADE_H3Q
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_FAMILY
+	string
+	default "BLADE_STEALTH"
+
+config MAINBOARD_PART_NUMBER
+	default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U
+	default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q
+
 # For now no way to choose the correct the available RAM
 config BOARD_RAZER_BLADE_STEALTH_KBL_16GB
 	bool "16GB RAM (4x MT52L1G32D4PG)"
@@ -27,13 +48,6 @@ config VGA_BIOS_ID
 	string
 	default "8086,5916"
 
-config MAINBOARD_FAMILY
-	string
-	default "BLADE_STEALTH"
-
-config MAINBOARD_PART_NUMBER
-	default "H2U"
-
 config MAINBOARD_VERSION
 	string
 	default "1.0"

src/mainboard/razer/blade_stealth_kbl/Kconfig.name

@@ -1,4 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-config BOARD_RAZER_BLADE_STEALTH_KBL
+config BOARD_RAZER_BLADE_H2U
-	bool "Razer Blade Stealth KabyLake (2016)"
+	bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")"
+
+config BOARD_RAZER_BLADE_H3Q
+	bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")"

src/mainboard/razer/blade_stealth_kbl/Makefile.mk

@@ -3,6 +3,8 @@
 subdirs-y += spd
 
 ramstage-y += ramstage.c
-ramstage-y += hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 
 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/razer/blade_stealth_kbl/board_info.txt

@@ -1,5 +1,5 @@
 Vendor name: RAZER
-Board name: Blade Stealth KabyLake (H2U)
+Board name: Blade Stealth KabyLake
 Category: laptop
 ROM package: SOIC8
 ROM protocol: SPI

src/mainboard/razer/blade_stealth_kbl/devicetree.cb

@@ -126,24 +126,6 @@ chip soc/intel/skylake
 
 	register "PcieRpHotPlug[4]" = "1"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
-		[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
-		[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
-		[6] = USB2_PORT_FLEX(OC2),	/* Camera */
-		[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
-		[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
-		[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
-		[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
-	}"
-
 	# PL1 override 25W
 	# PL2 override 44W
 	register "power_limits_config" = "{
@@ -191,9 +173,6 @@ chip soc/intel/skylake
 		device ref pcie_rp5	on  end
 		device ref pcie_rp9	on  end
 		device ref lpc_espi	on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
 			chip superio/ite/it8528e
 				device pnp 6e.1 off end
 				device pnp 6e.2 off end

src/mainboard/razer/blade_stealth_kbl/ramstage.c

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {

src/mainboard/razer/blade_stealth_kbl/spd/spd.h

@@ -4,7 +4,6 @@
 #define MAINBOARD_SPD_H
 
 #include <gpio.h>
-#include "../gpio.h"
 
 void mainboard_fill_dq_map_data(void *dq_map_ptr);
 void mainboard_fill_dqs_map_data(void *dqs_map_ptr);

src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt

@@ -0,0 +1,9 @@
+Vendor name: RAZER
+Board name: Blade Stealth KabyLake (H2U: RZ09-01962)
+Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2016

src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c

@@ -20,7 +20,7 @@ const u32 cim_verb_data[] = {
 	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
 	AZALIA_PIN_CFG(0, 0x21, 0x03211020),
 
-	/* Intel, KabylakeHDMI */
+	/* Intel, Kaby Lake HDMI */
 	0x8086280b, /* Vendor ID */
 	0x80860101, /* Subsystem ID */
 	4, /* Number of entries */

src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb

@@ -0,0 +1,31 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC1),	/* Type-A Port (right) */
+				[1] = USB2_PORT_MID(OC1),	/* Type-A Port (left) */
+				[2] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[3] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[4] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[5] = USB2_PORT_MID(OC1),	/* TODO Unknown. Maybe USBC? */
+				[6] = USB2_PORT_FLEX(OC2),	/* Camera */
+				[7] = USB2_PORT_FLEX(OC2),	/* Keyboard */
+				[8] = USB2_PORT_FLEX(OC2),	/* Touchscreen */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (left) */
+				[1] = USB3_PORT_DEFAULT(OC1),	/* Type-A Port (right) */
+				[5] = USB3_PORT_DEFAULT(OC1),	/* TODO Unknown. Maybe USBC? */
+			}"
+		end
+
+		device ref lpc_espi on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+	end
+end

src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt

@@ -0,0 +1,9 @@
+Vendor name: RAZER
+Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964)
+Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017

src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC298 */
+	0x10ec0298, /* Vendor ID */
+	0x1a586753, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x1a586753),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4075812d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+
+	/* Intel, Kaby Lake HDMI */
+	0x8086280b, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;

src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h

@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CFG_GPIO_H
+#define CFG_GPIO_H
+
+#include <gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	PAD_NC(GPP_A12, NONE),
+	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	PAD_CFG_GPO(GPP_A15, 0, DEEP),
+	PAD_CFG_GPO(GPP_A16, 0, DEEP),
+	PAD_CFG_GPO(GPP_A17, 0, DEEP),
+	PAD_CFG_GPO(GPP_A18, 0, DEEP),
+	PAD_CFG_GPO(GPP_A19, 0, DEEP),
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP),
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_GPO(GPP_B0, 0, DEEP),
+	PAD_CFG_GPO(GPP_B1, 0, DEEP),
+	PAD_CFG_GPO(GPP_B2, 0, DEEP),
+	PAD_CFG_GPO(GPP_B3, 0, DEEP),
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
+	PAD_NC(GPP_B19, NONE),
+	PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
+	PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP),
+	/* GPP_C6 - RESERVED */
+	/* GPP_C7 - RESERVED */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C10, 0, DEEP),
+	PAD_CFG_GPO(GPP_C11, 0, DEEP),
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	PAD_CFG_GPO(GPP_C13, 0, DEEP),
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	PAD_CFG_GPO(GPP_C23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 0, DEEP),
+	PAD_CFG_GPO(GPP_D1, 0, DEEP),
+	PAD_CFG_GPO(GPP_D2, 0, DEEP),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	PAD_CFG_GPO(GPP_D7, 0, DEEP),
+	PAD_CFG_GPO(GPP_D8, 0, DEEP),
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	PAD_CFG_GPO(GPP_D13, 0, DEEP),
+	PAD_CFG_GPO(GPP_D14, 0, DEEP),
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	PAD_CFG_GPO(GPP_D16, 0, DEEP),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+	PAD_CFG_GPO(GPP_D20, 0, DEEP),
+	PAD_CFG_GPO(GPP_D21, 0, DEEP),
+	PAD_CFG_GPO(GPP_D22, 0, DEEP),
+	PAD_CFG_GPO(GPP_D23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPO(GPP_E0, 0, DEEP),
+	PAD_CFG_GPO(GPP_E1, 0, DEEP),
+	PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),
+	PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E9, 0, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP),
+	PAD_NC(GPP_E12, NONE),
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT),
+	PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),
+	PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	PAD_CFG_NF(GPD0, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, DEEP),
+	PAD_NC(GPD8, NONE),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_GPO(GPP_F0, 0, DEEP),
+	PAD_CFG_GPO(GPP_F1, 0, DEEP),
+	PAD_CFG_GPO(GPP_F2, 0, DEEP),
+	PAD_CFG_GPO(GPP_F3, 0, DEEP),
+	PAD_CFG_GPO(GPP_F4, 0, DEEP),
+	PAD_CFG_GPO(GPP_F5, 0, DEEP),
+	PAD_CFG_GPO(GPP_F6, 0, DEEP),
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_GPO(GPP_F19, 0, DEEP),
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	PAD_CFG_GPO(GPP_F22, 0, DEEP),
+	PAD_CFG_GPO(GPP_F23, 0, DEEP),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPO(GPP_G0, 0, DEEP),
+	PAD_CFG_GPO(GPP_G1, 0, DEEP),
+	PAD_CFG_GPO(GPP_G2, 0, DEEP),
+	PAD_CFG_GPO(GPP_G3, 0, DEEP),
+	PAD_CFG_GPO(GPP_G4, 0, DEEP),
+	PAD_CFG_GPO(GPP_G5, 0, DEEP),
+	PAD_CFG_GPO(GPP_G6, 0, DEEP),
+	PAD_CFG_GPO(GPP_G7, 0, DEEP),
+};
+
+#endif /* CFG_GPIO_H */

src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb

@@ -0,0 +1,23 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	device domain 0 on
+		device ref south_xhci on
+			# NOTE: TYPE-C port is controlled by Intel Thunderbolt
+
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC0),	/* Type-A Port (right) */
+				[1] = USB2_PORT_MID(OC0),	/* Type-A Port (left) */
+				[5] = USB2_PORT_SHORT(OC2),	/* M.2 Slot (Bluetooth) */
+				[6] = USB2_PORT_FLEX(OC3),	/* Camera */
+				[7] = USB2_PORT_FLEX(OC3),	/* Keyboard */
+				[8] = USB2_PORT_FLEX(OC_SKIP),	/* Touchscreen */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (left) */
+				[1] = USB3_PORT_DEFAULT(OC0),	/* Type-A Port (right) */
+			}"
+		end
+	end
+end