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soc/intel/apollolake: Update Upd header files for FSP Label 143_10

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New UPDs added to header files as well as many comment fixes. Memory
infor is now defined in FspmUpd.h and added ability to skip CSE RBP
for coreboot. Removes some UPDs that are no longer available from
source.

BUG=chrome-os-partner:54677
BRANCH=none
TEST=built and tested with FSP 143_10 version

Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15459
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brandon Breitenstein
2016-06-24 10:41:39 -07:00
committed by Martin Roth
parent deed18627d
commit ba3d626cfb
3 changed files with 85 additions and 51 deletions
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6
src/soc/intel/apollolake/chip.c
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@@ -253,12 +253,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
/* Our defaults may not match FSP defaults, so set them explicitly */
silconfig->AcpiBase = ACPI_PMIO_BASE;
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR;
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
/* Disable setting of EISS bit in FSP. */