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libpayload: Add support for memory barriers

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Add support for memory barriers in arch {arm,arm64,x86}. This is required to
force strict CPU ordering. Definitions are based on FREEBSD atomic.h
definitions.

BUG=chrome-os-partner:31533
BRANCH=None
TEST=Memory barriers tested with ehci driver on arm64

Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552
Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213916
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
2014-08-24 22:47:20 -07:00
committed by Patrick Georgi
parent c88cca1c38
commit ba87e6cc94
5 changed files with 184 additions and 30 deletions
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18
payloads/libpayload/include/arm/arch/cache.h
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@ -70,24 +70,12 @@
/*
* Sync primitives
*/
/* data memory barrier */
static inline void dmb(void)
{
asm volatile ("dmb" : : : "memory");
}
#define dmb() asm volatile ("dmb" : : : "memory")
/* data sync barrier */
static inline void dsb(void)
{
asm volatile ("dsb" : : : "memory");
}
#define dsb() asm volatile ("dsb" : : : "memory")
/* instruction sync barrier */
static inline void isb(void)
{
asm volatile ("isb" : : : "memory");
}
#define isb() asm volatile ("isb" : : : "memory")
/*
* Low-level TLB maintenance operations