sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src: Replace min/max() with MIN/MAX()

Browse Source 
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2019-12-19 07:47:52 +01:00
committed by Patrick Georgi
parent 361a935332
commit ba9b504ec5
7 changed files with 34 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/mediatek/common/cbmem.c
View File

@@ -14,8 +14,8 @@
*/
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <stddef.h>
#include <stdlib.h>
#include <symbols.h>
#include <soc/emi.h>
@@ -23,5 +23,5 @@
void *cbmem_top_chipset(void)
{
return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
}

4
src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
View File

@@ -308,7 +308,7 @@ static u8 dqs_gw_fine_tune_calib(u32 channel, u8 fine_val)
int matches = 0, sum = 0;
/* fine tune range from 0 to 127 */
fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]);
fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]);
/* test gw fine tune */
for (i = 0; i < ARRAY_SIZE(delta); i++) {
@@ -443,7 +443,7 @@ void dramc_rankinctl_config(u32 channel,
if (is_dual_rank(channel, sdram_params)) {
/* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */
value = min(opt_gw_coarse_value[channel][0],
value = MIN(opt_gw_coarse_value[channel][0],
opt_gw_coarse_value[channel][1]) >> 2;
clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value);