pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
@ -45,29 +45,4 @@ config IRQ_SLOT_COUNT
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int
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int
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default 22
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default 22
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## Configuration for the PCMCIA-Cardbus controller.
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config TI_PCMCIA_CARDBUS_CMDR
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hex
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default 0x0107
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config TI_PCMCIA_CARDBUS_CLSR
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hex
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default 0x00
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config TI_PCMCIA_CARDBUS_CLTR
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hex
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default 0x40
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config TI_PCMCIA_CARDBUS_BCR
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hex
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default 0x07C0
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config TI_PCMCIA_CARDBUS_SCR
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hex
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default 0x08449060
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config TI_PCMCIA_CARDBUS_MRR
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hex
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default 0x00007522
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endif # BOARD_NOKIA_IP530
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endif # BOARD_NOKIA_IP530
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@ -28,6 +28,17 @@ chip northbridge/intel/i440bx # Northbridge
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device pci 0.0 on end # Host bridge
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci f.0 on
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chip southbridge/ti/pci1x2x
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device pci 00.0 on
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end
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register "cltr" = "0x40"
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register "bcr" = "0x7c0"
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register "scr" = "0x08449060"
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register "mrr" = "0x00007522"
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end
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end
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device pci 7.0 on # ISA bridge
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device pci 7.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
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device pnp 3f0.0 off end # Floppy (No connector)
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device pnp 3f0.0 off end # Floppy (No connector)
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13
src/southbridge/ti/pci1x2x/chip.h
Normal file
13
src/southbridge/ti/pci1x2x/chip.h
Normal file
@ -0,0 +1,13 @@
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#ifndef SOUTHBRIDGE_TI_PCI1X2X_H
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#define SOUTHBRIDGE_TI_PCI1X2X_H
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extern struct chip_operations southbridge_ti_pci1x2x_ops;
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struct southbridge_ti_pci1x2x_config {
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int scr;
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int mrr;
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int clsr;
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int cltr;
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int bcr;
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};
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#endif
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@ -23,44 +23,41 @@
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <console/console.h>
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#include "chip.h"
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#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
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!defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
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#error "you must supply these values in your mainboard-specific Kconfig file"
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#endif
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static void ti_pci1x2y_init(struct device *dev)
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static void ti_pci1x2y_init(struct device *dev)
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{
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{
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printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
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/* Command (offset 04) */
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printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
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pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
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struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
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/* Cache Line Size (offset 0x0C) */
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pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
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if (conf) {
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/* CardBus latency timer (offset 0x1B) */
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/* Cache Line Size (offset 0x0C) */
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pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
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pci_write_config8(dev, 0x0C, conf->clsr);
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/* Bridge control (offset 0x3E) */
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/* CardBus latency timer (offset 0x1B) */
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pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
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pci_write_config8(dev, 0x1B, conf->cltr);
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/* Bridge control (offset 0x3E) */
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pci_write_config16(dev, 0x3E, conf->bcr);
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}
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/*
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/*
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* Enable change sub-vendor ID. Clear the bit 5 to enable to write
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* Enable change sub-vendor ID. Clear the bit 5 to enable to write
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* to the sub-vendor/device ids at 40 and 42.
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* to the sub-vendor/device ids at 40 and 42.
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*/
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*/
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pci_write_config32(dev, 0x80, 0x10);
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pci_write_config32(dev, 0x80, 0x10);
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pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
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pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
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/* Now write the correct value for SCR. */
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/* System control (offset 0x80) */
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if (conf) {
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pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
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/* Now write the correct value for SCR. */
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/* Multifunction routing */
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/* System control (offset 0x80) */
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pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
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pci_write_config32(dev, 0x80, conf->scr);
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/* Multifunction routing */
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pci_write_config32(dev, 0x8C, conf->mrr);
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}
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/* Set the device control register (0x92) accordingly. */
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/* Set the device control register (0x92) accordingly. */
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pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
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pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
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}
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}
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static struct device_operations ti_pci1x2y_ops = {
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struct device_operations southbridge_ti_pci1x2x_pciops = {
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.read_resources = NULL, //pci_dev_read_resources,
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.read_resources = NULL, //pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable_resources = pci_dev_enable_resources,
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@ -69,19 +66,23 @@ static struct device_operations ti_pci1x2y_ops = {
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};
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};
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static const struct pci_driver ti_pci1225_driver __pci_driver = {
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static const struct pci_driver ti_pci1225_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.ops = &southbridge_ti_pci1x2x_pciops,
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.vendor = PCI_VENDOR_ID_TI,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1225,
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.device = PCI_DEVICE_ID_TI_1225,
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};
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};
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static const struct pci_driver ti_pci1420_driver __pci_driver = {
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static const struct pci_driver ti_pci1420_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.ops = &southbridge_ti_pci1x2x_pciops,
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.vendor = PCI_VENDOR_ID_TI,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1420,
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.device = PCI_DEVICE_ID_TI_1420,
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};
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};
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static const struct pci_driver ti_pci1520_driver __pci_driver = {
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static const struct pci_driver ti_pci1520_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.ops = &southbridge_ti_pci1x2x_pciops,
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.vendor = PCI_VENDOR_ID_TI,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1520,
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.device = PCI_DEVICE_ID_TI_1520,
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};
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};
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struct chip_operations southbridge_ti_pci1x2x_ops = {
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CHIP_NAME("TI PCI1x2x Cardbus controller")
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};
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