cbfs: Enable CBFS mcache on most chipsets

This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.

Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/asus/p5gc-mx/Kconfig

@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_512
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select INTEL_GMA_HAVE_VBT
+	select NO_CBFS_MCACHE
 
 config MAINBOARD_DIR
 	string

src/mainboard/emulation/qemu-aarch64/memlayout.ld

@@ -19,7 +19,8 @@ SECTIONS
 	REGION(secram, 0xe000000, 0x1000000, 4096)
 	DRAM_START(0x40000000)
 	BOOTBLOCK(0x60010000, 64K)
-	STACK(0x60020000, 62K)
+	STACK(0x60020000, 54K)
+	CBFS_MCACHE(0x6002D800, 8K)
 	FMAP_CACHE(0x6002F800, 2K)
         TIMESTAMP(0x60030000, 1K)
 	ROMSTAGE(0x60031000, 128K)

src/mainboard/emulation/qemu-armv7/memlayout.ld

@@ -35,6 +35,7 @@ SECTIONS
 	BOOTBLOCK(0x60010000, 128K)
 	FMAP_CACHE(0x60030000, 4K)
 	TIMESTAMP(0x60031000, 1K)
+	CBFS_MCACHE(0x60031400, 7K)
 	/* TODO: Implement MMU support and move TTB to a better location. */
 	TTB(0x60034000, 16K)
 	ROMSTAGE(0x60038000, 128K)

src/mainboard/emulation/qemu-power8/memlayout.ld

@@ -13,5 +13,6 @@ SECTIONS
 	STACK(0x40000, 0x3ff00)
 	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
 	FMAP_CACHE(0x82000, 2K)
+	CBFS_MCACHE(0x82800, 8K)
 	RAMSTAGE(0x100000, 16M)
 }

src/mainboard/emulation/qemu-riscv/memlayout.ld

@@ -25,6 +25,7 @@ SECTIONS
 #endif
 	PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K)
 	FMAP_CACHE(STAGES_START + 136K, 2K)
+	CBFS_MCACHE(STAGES_START + 138K, 8K)
 	RAMSTAGE(STAGES_START + 200K, 16M)
 	STACK(STAGES_START + 200K + 16M, 4K)
 }

src/mainboard/emulation/spike-riscv/memlayout.ld

@@ -12,7 +12,8 @@ SECTIONS
 	BOOTBLOCK(START, 64K)
 	STACK(START + 8M, 4K)
 	FMAP_CACHE(START + 8M + 4K, 2K)
-	/* hole at (START + 8M + 6K, 58K) */
+	CBFS_MCACHE(START + 8M + 6K, 8K)
+	/* hole at (START + 8M + 14K, 50K) */
 	ROMSTAGE(START + 8M + 64K, 128K)
 	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
 	RAMSTAGE(START + 8M + 200K, 256K)

src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig

@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select REALTEK_8168_RESET if BOARD_GIGABYTE_GA_945GCM_S2L
 	select INTEL_GMA_HAVE_VBT
+	select NO_CBFS_MCACHE
 
 config MAINBOARD_DIR
 	string

src/mainboard/google/octopus/Kconfig

@@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select NO_BOOTBLOCK_CONSOLE
 	select NO_FMAP_CACHE
+	select NO_CBFS_MCACHE
 
 if BOARD_GOOGLE_BASEBOARD_OCTOPUS
 

src/mainboard/lenovo/t400/Kconfig

@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500
 	select INTEL_GMA_HAVE_VBT
+	select NO_CBFS_MCACHE
 
 config VBOOT
 	select VBOOT_VBNV_CMOS