cbfs: Enable CBFS mcache on most chipsets

This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.

Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/northbridge/intel/e7505/Kconfig

@@ -9,5 +9,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select NO_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
+	select NO_CBFS_MCACHE
 
 endif

src/northbridge/intel/i440bx/Kconfig

@@ -5,6 +5,7 @@ config NORTHBRIDGE_INTEL_I440BX
 	select NO_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
 	select NO_BOOTBLOCK_CONSOLE
+	select NO_CBFS_MCACHE
 
 config SDRAMPWR_4DIMM
 	bool

src/northbridge/intel/pineview/Kconfig

@@ -14,6 +14,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_GMA_ACPI
 	select PARALLEL_MP
+	select NO_CBFS_MCACHE
 
 config VGA_BIOS_ID
 	string

src/northbridge/intel/x4x/Kconfig

@@ -13,6 +13,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select CACHE_MRC_SETTINGS
 	select PARALLEL_MP
 	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
+	select NO_CBFS_MCACHE
 
 config CBFS_SIZE
 	hex