post_code: add post code for invalid vendor binary
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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committed by
Duncan Laurie
parent
1835bf0fd4
commit
bb41aba0d8
@ -195,9 +195,6 @@ void raminit(struct romstage_params *params)
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}
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#if CONFIG(DISPLAY_HOBS)
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if (hob_list_ptr == NULL)
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die("ERROR - HOB pointer is NULL!\n");
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/*
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* Verify that FSP is generating the required HOBs:
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* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
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@ -244,7 +241,10 @@ void raminit(struct romstage_params *params)
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"ERROR - Missing one or more required FSP HOBs!\n");
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/* Display the HOBs */
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print_hob_type_structure(0, hob_list_ptr);
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if (hob_list_ptr != NULL)
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print_hob_type_structure(0, hob_list_ptr);
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else
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printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n");
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#endif
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/* Get the address of the CBMEM region for the FSP reserved memory */
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@ -274,14 +274,16 @@ void raminit(struct romstage_params *params)
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printk(BIOS_DEBUG,
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"0x%08x: Chipset reserved bytes reported by FSP\n",
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(unsigned int)delta_bytes);
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die("Please verify the chipset reserved size\n");
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"Please verify the chipset reserved size\n");
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}
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#endif
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}
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/* Verify the FSP 1.1 HOB interface */
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if (fsp_verification_failure)
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die("ERROR - coreboot's requirements not met by FSP binary!\n");
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die_with_post_code(POST_INVALID_VENDOR_BINARY,
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"ERROR - coreboot's requirements not met by FSP binary!\n");
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/* Display the memory configuration */
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report_memory_config();
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