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post_code: add post code for invalid vendor binary

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Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Keith Short
2019-05-16 14:07:43 -06:00
committed by Duncan Laurie
parent 1835bf0fd4
commit bb41aba0d8
9 changed files with 31 additions and 13 deletions
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6
src/drivers/intel/fsp2_0/memory_init.c
View File

@@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPM signature!\n");
/* Copy the default values from the UPD area */
memcpy(&fspm_upd, upd, sizeof(fspm_upd));
@@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
die("FSPM_ARCH_UPD not found!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);

3
src/drivers/intel/fsp2_0/silicon_init.c
View File

@@ -33,7 +33,8 @@ static void do_silicon_init(struct fsp_header *hdr)
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
die("Invalid FSPS signature\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPS signature\n");
upd = xmalloc(sizeof(FSPS_UPD));