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post_code: add post code for invalid vendor binary

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Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Keith Short
2019-05-16 14:07:43 -06:00
committed by Duncan Laurie
parent 1835bf0fd4
commit bb41aba0d8
9 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/fsp_baytrail/romstage/romstage.c
View File

@@ -208,7 +208,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************

3
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View File

@@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************