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post_code: add post code for invalid vendor binary

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Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Keith Short
2019-05-16 14:07:43 -06:00
committed by Duncan Laurie
parent 1835bf0fd4
commit bb41aba0d8
9 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/POSTCODES
View File

@@ -18,6 +18,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
0x89 Devices have been enabled
0xe0 Boot media (e.g. SPI ROM) is corrupt
0xe1 Resource stored within CBFS is corrupt
0xe2 Vendor binary (e.g. FSP) generated a fatal error
0xf8 Entry into elf boot
0xf3 Jumping to payload

12
src/drivers/intel/fsp1_1/raminit.c
View File

@@ -195,9 +195,6 @@ void raminit(struct romstage_params *params)
}
#if CONFIG(DISPLAY_HOBS)
if (hob_list_ptr == NULL)
die("ERROR - HOB pointer is NULL!\n");
/*
* Verify that FSP is generating the required HOBs:
* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
@@ -244,7 +241,10 @@ void raminit(struct romstage_params *params)
"ERROR - Missing one or more required FSP HOBs!\n");
/* Display the HOBs */
if (hob_list_ptr != NULL)
print_hob_type_structure(0, hob_list_ptr);
else
printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n");
#endif
/* Get the address of the CBMEM region for the FSP reserved memory */
@@ -274,14 +274,16 @@ void raminit(struct romstage_params *params)
printk(BIOS_DEBUG,
"0x%08x: Chipset reserved bytes reported by FSP\n",
(unsigned int)delta_bytes);
die("Please verify the chipset reserved size\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Please verify the chipset reserved size\n");
}
#endif
}
/* Verify the FSP 1.1 HOB interface */
if (fsp_verification_failure)
die("ERROR - coreboot's requirements not met by FSP binary!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"ERROR - coreboot's requirements not met by FSP binary!\n");
/* Display the memory configuration */
report_memory_config();

6
src/drivers/intel/fsp2_0/memory_init.c
View File

@@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPM signature!\n");
/* Copy the default values from the UPD area */
memcpy(&fspm_upd, upd, sizeof(fspm_upd));
@@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
die("FSPM_ARCH_UPD not found!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);

3
src/drivers/intel/fsp2_0/silicon_init.c
View File

@@ -33,7 +33,8 @@ static void do_silicon_init(struct fsp_header *hdr)
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
die("Invalid FSPS signature\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPS signature\n");
upd = xmalloc(sizeof(FSPS_UPD));

8
src/include/console/post_codes.h
View File

@@ -332,6 +332,14 @@
*/
#define POST_INVALID_CBFS 0xe1
/**
* \brief Vendor binary error
*
* Set if firmware failed to find or validate a vendor binary, or the binary
* generated a fatal error.
*/
#define POST_INVALID_VENDOR_BINARY 0xe2
/**
* \brief TPM failure
*

3
src/northbridge/intel/haswell/raminit.c
View File

@@ -166,7 +166,8 @@ void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
die("Nonzero MRC return value.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");

3
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@@ -235,7 +235,8 @@ void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
die("Nonzero MRC return value.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");

3
src/soc/intel/fsp_baytrail/romstage/romstage.c
View File

@@ -208,7 +208,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************

3
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View File

@@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die("Uh Oh! fsp_early_init should not return here.\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************