mb/google/brox/var/greenbayupoc: Update devicetree and gpio settings
Based on latest schematics GREENBAY_0412.SCH update the gpio and devicetree settings. BUG=b:326413034 TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT Cq-Depend:chrome-internal:7218819 Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455 Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
This commit is contained in:
Eren Peng
Felix Held
parent
d05611d264
commit
bb616ca483
@ -70,6 +70,7 @@ config BOARD_GOOGLE_LOTSO
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config BOARD_GOOGLE_GREENBAYUPOC
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select BOARD_GOOGLE_BASEBOARD_BROX
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select MEMORY_SODIMM
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if BOARD_GOOGLE_BROX_COMMON
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@ -1,3 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-y += gpio.c
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ramstage-y += ramstage.c
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139
src/mainboard/google/brox/variants/greenbayupoc/gpio.c
Normal file
139
src/mainboard/google/brox/variants/greenbayupoc/gpio.c
Normal file
@ -0,0 +1,139 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This header block is used to supply information to arbitrage, a
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* google-internal tool. Updating it incorrectly will lead to issues,
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* so please don't update it unless a change is specifically required.
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* BaseID: E3110FFB1FCDA587
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* Overrides: None
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */
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PAD_NC(GPP_A18, NONE),
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/* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX
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* NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */
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PAD_NC(GPP_D9, NONE),
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/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX
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* NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */
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PAD_NC(GPP_D10, NONE),
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/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */
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PAD_NC(GPP_E4, NONE),
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
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PAD_NC(GPP_E12, NONE),
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/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
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PAD_NC(GPP_E13, NONE),
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/* GPP_E15 : SRCCLK_OE8_L ==> NC */
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PAD_NC(GPP_E15, NONE),
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/* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */
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PAD_NC(GPP_H15, NONE),
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/* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */
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PAD_NC(GPP_H17, NONE),
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/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
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PAD_NC(GPP_S0, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
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PAD_NC(GPP_D11, NONE),
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/* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
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PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
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/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_F9, 0, DEEP),
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/* F21 : EXT_PWR_GATE2# ==> NC */
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PAD_NC(GPP_F21, NONE),
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/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
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/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
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/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
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PAD_NC(GPP_S0, NONE),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */
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PAD_NC(GPP_E12, NONE),
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/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */
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PAD_NC(GPP_E13, NONE),
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/* GPP_E15 : SRCCLK_OE8_L ==> NC */
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PAD_NC(GPP_E15, NONE),
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/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_F7, 1, PLTRST),
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/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_F9, 1, DEEP),
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/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_F17, 0, DEEP),
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/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */
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PAD_NC(GPP_S0, NONE),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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@ -1,14 +1,201 @@
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fw_config
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field STORAGE 0 1
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field RETIMER 0 1
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option RETIMER_UNKNOWN 0
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option RETIMER_BYPASS 1
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end
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field STORAGE 2 3
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option STORAGE_UNKNOWN 0
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option STORAGE_UFS 1
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option STORAGE_NVME 2
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option STORAGE_NVME 1
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option STORAGE_UFS 2
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end
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field WIFI 4
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option WIFI_CNVI_WIFI 0
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option WIFI_BT_PCIE 1
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end
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field UFC 5
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option UFC_NONE 0
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option UFC_USB 1
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end
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field AUDIO 6 7
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option AUDIO_UNKNOWN 0
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option AUDIO_REALTEK_ALC3247 1
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end
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end
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chip soc/intel/alderlake
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register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI)
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device domain 0 on
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device ref igpu on
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chip drivers/gfx/generic
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register "device_count" = "6"
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# DDIA for eDP
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register "device[0].name" = ""LCD0""
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register "device[0].type" = "panel"
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# DDIB for HDMI
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# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
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register "device[1].name" = ""DD01""
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# TCP0 (DP-1) for port C0
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register "device[2].name" = ""DD02""
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register "device[2].use_pld" = "true"
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register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
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register "device[3].name" = ""DD03""
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# TCP2 (DP-3) for port C2
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register "device[4].name" = ""DD04""
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register "device[4].use_pld" = "true"
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register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
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register "device[5].name" = ""DD05""
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device generic 0 on end
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end
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end # Integrated Graphics Device
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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register "has_power_resource" = "1"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (DCI)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "has_power_resource" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (DCI)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
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device ref usb3_port3 on end
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end
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end
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end
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end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 3
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 3,
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.clk_src = 3,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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probe STORAGE STORAGE_NVME
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probe STORAGE STORAGE_UNKNOWN
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end
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device ref pcie_rp5 on
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW0_03"
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register "add_acpi_dma_property" = "true"
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device pci 00.0 on
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probe WIFI WIFI_BT_PCIE
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end
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end
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
|
||||
register "srcclk_pin" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_BT_PCIE
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI WIFI_CNVI_WIFI
|
||||
end
|
||||
device ref smbus on end
|
||||
end
|
||||
|
||||
|
||||
18
src/mainboard/google/brox/variants/greenbayupoc/ramstage.c
Normal file
18
src/mainboard/google/brox/variants/greenbayupoc/ramstage.c
Normal file
@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
const struct cpu_power_limits limits[] = {
|
||||
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
|
||||
/* All values are for performance config as per document #686872 */
|
||||
{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
|
||||
};
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
size_t total_entries = ARRAY_SIZE(limits);
|
||||
variant_update_power_limits(limits, total_entries);
|
||||
}
|
||||
20
src/mainboard/google/brox/variants/greenbayupoc/variant.c
Normal file
20
src/mainboard/google/brox/variants/greenbayupoc/variant.c
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) {
|
||||
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
|
||||
config->cnvi_bt_core = true;
|
||||
}
|
||||
}
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user