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nb/intel/x4x: Define and use MMCONF_BUS_NUMBER

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Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.

Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-01-20 13:23:18 +01:00
parent 1318ab475d
commit bbc80f4405
7 changed files with 21 additions and 54 deletions
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14
src/northbridge/intel/x4x/bootblock.c
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@@ -2,15 +2,27 @@
#include <arch/bootblock.h>
#include <arch/mmio.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "x4x.h"
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}