diff --git a/MAINTAINERS b/MAINTAINERS index 4f643b2f3c..880c4aa445 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,19 +233,19 @@ F: src/mainboard/facebook/monolith/ GETAC P470 MAINBOARD M: Patrick Georgi S: Maintained -F: src/mainboard/getac/p470 +F: src/mainboard/getac/p470/ GIGABYTE GA-G41M-ES2L MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/gigabyte/ga-g41m-es2l +F: src/mainboard/gigabyte/ga-g41m-es2l/ GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons S: Maintained -F: src/mainboard/gigabyte/ga-h61m-series +F: src/mainboard/gigabyte/ga-h61m-series/ @@ -273,7 +273,7 @@ F: src/mainboard/google/stout/ INTEL D510MO MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/intel/d510mo +F: src/mainboard/intel/d510mo/ INTEL STRAGO MAINBOARD M: Hannah Williams @@ -314,7 +314,7 @@ LIBRETREND LT1000 MAINBOARD M: Piotr Król M: Michał Żygowski S: Maintained -F: src/mainboard/libretrend/lt1000 +F: src/mainboard/libretrend/lt1000/ OCP DELTALAKE MAINBOARD @@ -325,7 +325,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Supported -F: src/mainboard/ocp/deltalake +F: src/mainboard/ocp/deltalake/ OCP TIOGAPASS MAINBOARD M: Jonathan Zhang @@ -335,7 +335,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Maintained -F: src/mainboard/ocp/tiogapass +F: src/mainboard/ocp/tiogapass/ @@ -375,14 +375,14 @@ PRODRIVE HERMES MAINBOARD M: Christian Walter M: Patrick Rudolph S: Maintained -F: src/mainboard/prodrive/hermes +F: src/mainboard/prodrive/hermes/ PURISM MAINBOARDS M: Matt DeVillier S: Supported -F: src/mainboard/purism +F: src/mainboard/purism/ @@ -556,8 +556,8 @@ M: Marshall Dawson M: Felix Held M: Jason Glenesk S: Maintained -F: src/soc/amd/picasso -F: src/vendorcode/amd/fsp/picasso +F: src/soc/amd/picasso/ +F: src/vendorcode/amd/fsp/picasso/ INTEL APOLLOLAKE_SOC M: Andrey Petrov @@ -569,8 +569,8 @@ M: Piotr Król M: Michał Żygowski M: Frans Hendriks S: Maintained -F: /src/soc/intel/braswell -F: /src/vendorcode/intel/fsp/fsp1_1/braswell +F: /src/soc/intel/braswell/ +F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang @@ -581,13 +581,13 @@ M: Ryback Hung < M: Bryant Ou S: Supported F: src/soc/intel/xeon_sp -F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp -F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ MEDIATEK SOCS M: Hung-Te Lin S: Supported -F: src/soc/mediatek +F: src/soc/mediatek/ ORPHANED ARM SOCS S: Orphaned @@ -615,13 +615,13 @@ F: payloads/coreinfo/ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer M: Martin Roth -F: payloads/external +F: payloads/external/ LINUXBOOT PAYLOAD INTEGRATION M: Christian Walter M: Marcello Sylvester Bauer S: Supported -F: payloads/external/LinuxBoot +F: payloads/external/LinuxBoot/ ################################################################################ # Utilities @@ -751,7 +751,7 @@ TPM SUPPORT M: Christian Walter S: Supported F: src/drivers/*/tpm/ -F: src/security/tpm +F: src/security/tpm/ SUPERIOS & SUPERIOTOOL M: Felix Held @@ -769,7 +769,7 @@ ELTAN VENDORCODE M: Frans Hendriks M: Wim Vervoorn S: Maintained -F: src/vendorcode/eltan +F: src/vendorcode/eltan/ MISSING: TIMERS / DELAYS diff --git a/Makefile.inc b/Makefile.inc index fafb9ecd0d..95846a75c7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -338,7 +338,7 @@ cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ printf " CC+STRIP $(@)\n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ - $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ + $(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \ rm -f $(2).tmp) \ $(eval DEPENDENCIES += $(2).d) diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a5ed..5173ae5a0c 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,6 +43,7 @@ * if the revision of the update is newer than what is installed */ +.code32 .section .text .global update_bsp_microcode diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc929..70255173f1 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -16,7 +16,12 @@ #endif #include +#if defined(__RAMSTAGE__) +#include +#else #include +#endif + setup_longmode: /* Get page table address */ @@ -42,7 +47,12 @@ setup_longmode: movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ +#if defined(__RAMSTAGE__) + ljmp $RAM_CODE_SEG64, $__longmode_start +#else ljmp $ROM_CODE_SEG64, $__longmode_start + +#endif .code64 __longmode_start: diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52a6d..07e63f42de 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -7,6 +7,7 @@ #include +.code32 .section .text .global check_mtrr diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 054f30d2c4..61d9e34466 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -5,6 +5,8 @@ #include #include +#define __RAMSTAGE__ + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -192,11 +194,24 @@ load_msr: mov %eax, %cr4 #endif +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ +#include + + mov %rsi, %rdi /* cpu_num */ + + movl c_handler, %eax + call *%rax +#else /* c_handler(cpu_num), preserve proper stack alignment */ sub $12, %esp push %esi /* cpu_num */ + mov c_handler, %eax call *%eax +#endif + + halt_jump: hlt jmp halt_jump diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index bf974ffffe..bb30d20acd 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -32,7 +32,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) return -ENOMEM; } - fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095); ast_set_offset_reg(crtc); ast_set_start_address_crt1(ast, fb->mmio_addr); @@ -230,7 +230,7 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags) set_vbe_mode_info_valid(&edid, fb.mmio_addr); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); return 0; } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf1281e..ee04630ca1 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -57,7 +57,7 @@ static void fsp_notify(enum fsp_notify_phase phase) static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index d12274f8c0..ce2455f30b 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -82,7 +82,7 @@ Device (EC0) Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power -} + } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68cd0e..bad9d9c53e 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index b779630d56..67766217e8 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -21,7 +21,7 @@ config FMDFILE config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" default n - select PICASSO_LPC_IOMUX + select MANDOLIN_LPC select SUPERIO_SMSC_SIO1036 help AMD's debug card contains an SMSC SIO1036 device which provides an @@ -111,7 +111,7 @@ config MANDOLIN_IOMUX_USE_EMMC endchoice endif # !AMD_LPC_DEBUG_CARD -config PICASSO_LPC_IOMUX +config MANDOLIN_LPC bool default y if MANDOLIN_IOMUX_USE_LPC help diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 778701834f..795a28fde2 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -6,7 +6,7 @@ bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c -ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) +ifneq ($(CONFIG_MANDOLIN_LPC),y) ramstage-y += emmc_gpio.c endif diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 247616cff7..b509282f8b 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -111,13 +111,13 @@ static void mainboard_init(void *chip_info) { struct soc_amd_picasso_config *cfg = config_of_soc(); - if (!CONFIG(PICASSO_LPC_IOMUX)) + if (!CONFIG(MANDOLIN_LPC)) cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ - if (CONFIG(PICASSO_LPC_IOMUX)) + if (CONFIG(MANDOLIN_LPC)) printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); else mainboard_program_emmc_gpios(); diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 1553a3af54..f2e4adc1cc 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -106,6 +106,7 @@ config MAINBOARD_PART_NUMBER default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI default "Voema" if BOARD_GOOGLE_VOEMA + default "Drobit" if BOARD_GOOGLE_DROBIT config MAX_CPUS int @@ -146,6 +147,7 @@ config VARIANT_DIR default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI default "voema" if BOARD_GOOGLE_VOEMA + default "drobit" if BOARD_GOOGLE_DROBIT config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 0f9b6e287c..7536dc5eb1 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -89,3 +89,7 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_DROBIT + bool "-> Drobit" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f51b3af398 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 7c2b95b6ec..be43e8a02d 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE 64K + RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000000..b8bd6dcd9b --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,499 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C1.CAM0, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C1) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_R5) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_R5) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + /* Pull RST low */ + CTXS(GPP_R5) + /* Pull PWREN low */ + CTXS(GPP_B23) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_E16) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_E15) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_E15) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + /* Pull RST low */ + CTXS(GPP_E15) + /* Pull PWREN low */ + CTXS(GPP_E16) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 80edb92003..f2f768a8be 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,6 +51,12 @@ chip soc/intel/alderlake register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" + # Enable PCH PCIE RP 8 using free running CLK (0x80) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieRpClkReqDetect[7]" = "1" + # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" @@ -245,7 +251,7 @@ chip soc/intel/alderlake device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 + device pci 1c.7 on end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 on end # RP11 diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index d4fb7a4273..6e7ccd1d7c 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -27,6 +27,9 @@ DefinitionBlock( #include } + /* Camera */ + #include + #if CONFIG(CHROMEOS) /* Chrome OS specific */ #include diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 89e6f5826b..8ff6fcdbe3 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -26,8 +26,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* M.2 SSD_2 Reset */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM1-IRQ */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* CAM_STROBE */ PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Audio Codec INT N */ @@ -72,7 +70,19 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* THC0 SPI1 CLK */ @@ -134,22 +144,16 @@ static const struct pad_config gpio_table[] = { /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -158,34 +162,26 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), @@ -196,15 +192,6 @@ static const struct pad_config gpio_table[] = { /* I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S1_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* I2S1_RXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - /* I2S2_SCLK */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SFRM */ @@ -251,10 +238,6 @@ static const struct pad_config gpio_table[] = { /* USB2 OC0 pins */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* USB2 OC1 pins */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* USB2 OC2 pins */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB2 OC3 pins */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), @@ -263,8 +246,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h index 4303faf0d2..c01829936d 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -56,9 +56,6 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index b61276c0c1..de0adf6cff 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,7 +12,4 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* EC sync IRQ */ -#define EC_SYNC_IRQ GPP_A15_IRQ - #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 537e62451a..9cb8640860 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -14,6 +14,8 @@ enum adl_boardid { ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5 = 0x13, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 5d374db2a6..80ec14aa17 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -22,29 +22,19 @@ static const struct mb_cfg ddr4_mem_config = { static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ - 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ - { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ - 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ - { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ - 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ - { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ - 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ - { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ - 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ - { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ - 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ - { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ - 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ - { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ - 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, + { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, + { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, + { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, + { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, + { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, + { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, + { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, .dq_pins_interleaved = false, @@ -54,6 +44,34 @@ static const struct mb_cfg lpddr4_mem_config = { .UserBd = BOARD_TYPE_MOBILE, }; +static const struct mb_cfg lp5_mem_config = { + + /* DQ byte map */ + .dq_map = { + { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, + { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, + { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, + { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, + { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, + { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, + { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, + { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = false, /* Early Command Training */ + + .lp5_ccc_config = 0xff, + + .UserBd = BOARD_TYPE_MOBILE, +}; + static const struct mb_cfg ddr5_mem_config = { /* Baseboard uses only 100ohm Rcomp resistors */ .rcomp_resistor = {100, 100, 100}, @@ -81,6 +99,8 @@ const struct mb_cfg *variant_memory_params(void) return &ddr4_mem_config; case ADL_P_DDR5: return &ddr5_mem_config; + case ADL_P_LP5: + return &lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 672c59743e..2f03cb4e84 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lpddr4_spd_info = { + const struct spd_info lp4_lp5_spd_info = { .read_type = READ_SPD_CBFS, .spd_spec.spd_index = get_spd_index(), }; @@ -56,7 +56,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) break; case ADL_P_LP4_1: case ADL_P_LP4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + case ADL_P_LP5: + memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 1218a76690..10ce42ef4c 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -1,4 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = adlrvp_lp4 #0b000 -SPD_SOURCES += empty # 0b001 +SPD_SOURCES = adlrvp_lp4 # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += empty # 0b002 +SPD_SOURCES += adlrvp_lp5 # 0b003 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d0ec..e1d338edbc 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex new file mode 100644 index 0000000000..2f2a31a33d --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 57be7f19e9..e4e0b242e0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,37 +1,38 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x12ffc0 - RW_FWID_A@0x13ffc0 0x40 - ME_RW_A(CBFS)@0x140000 0x190000 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x12ffc0 - RW_FWID_B@0x13ffc0 0x40 - ME_RW_B(CBFS)@0x140000 0x190000 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x30000 - WP_RO@0x600000 0x400000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index 19518f74a4..771c6aae7b 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig index 1705b9109c..f53746d7a9 100644 --- a/src/mainboard/kontron/mal10/Kconfig +++ b/src/mainboard/kontron/mal10/Kconfig @@ -2,18 +2,18 @@ if BOARD_KONTRON_COME_MAL10 config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_16384 - select ONBOARD_VGA_IS_PRIMARY - select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_CRB_TPM - select EC_KONTRON_KEMPLD - select DRIVERS_I2C_NCT7802Y + select MAINBOARD_HAS_LIBGFXINIT + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index f1f93bf4fc..674b209317 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/carrier/gpio.h" +#include static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 1e88e38e5f..3986776870 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/variant/gpio.h" +#include static const struct pad_config gpio_table[] = { /* SPI */ diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 96b006020b..72a74daecc 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -180,6 +180,30 @@ static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) } } +static const struct port_information smbios_type8_info[] = { + { + .internal_reference_designator = "JCN18 - CPU MIPI60", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN32 - TPM_CONN", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN7 - USB type C", + .internal_connector_type = CONN_USB_TYPE_C, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, +}; + static int create_smbios_type9(int *handle, unsigned long *current) { int index; @@ -281,6 +305,13 @@ static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long { int len = 0; + // add port information + len += smbios_write_type8( + current, handle, + smbios_type8_info, + ARRAY_SIZE(smbios_type8_info) + ); + len += create_smbios_type9(handle, current); return len; diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc index abeedf3a85..c57c0a50dc 100644 --- a/src/mainboard/siemens/chili/Makefile.inc +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include romstage-y += romstage.c diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c index bc0eb7d9ff..7d9b6f2495 100644 --- a/src/mainboard/siemens/chili/ec.c +++ b/src/mainboard/siemens/chili/ec.c @@ -4,10 +4,9 @@ #include #include #include +#include #include -#include "ec.h" - #define EC_STATUS 0x50 #define EC_RUNNING (1 << 1) #define EC_DEVICE_CONTROL_1 0x80 diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/include/mainboard/ec.h similarity index 100% rename from src/mainboard/siemens/chili/ec.h rename to src/mainboard/siemens/chili/include/mainboard/ec.h diff --git a/src/mainboard/siemens/chili/include/mainboard/gpio.h b/src/mainboard/siemens/chili/include/mainboard/gpio.h new file mode 100644 index 0000000000..ef2a21c418 --- /dev/null +++ b/src/mainboard/siemens/chili/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/include/variant.h similarity index 75% rename from src/mainboard/siemens/chili/variant.h rename to src/mainboard/siemens/chili/include/variant.h index 2bbe7d7926..1d97728513 100644 --- a/src/mainboard/siemens/chili/variant.h +++ b/src/mainboard/siemens/chili/include/variant.h @@ -7,6 +7,4 @@ void variant_romstage_params(FSPM_UPD *); -const struct pad_config *variant_gpio_table(size_t *num); - #endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c index 91395eac07..c1d1a1d941 100644 --- a/src/mainboard/siemens/chili/mainboard.c +++ b/src/mainboard/siemens/chili/mainboard.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include - -#include "ec.h" +#include static void mainboard_dev_init(struct device *dev) { diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index c1ec7e4982..7453fa58e4 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include - -#include "variant.h" - -static void mainboard_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} +#include void mainboard_memory_init_params(FSPM_UPD *memupd) { @@ -40,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) variant_romstage_params(memupd); - mainboard_init(); + mainboard_configure_gpios(); } __weak void variant_romstage_params(FSPM_UPD *const mupd) diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c index 65ea037a3a..9d459ccc2a 100644 --- a/src/mainboard/siemens/chili/variants/base/gpio.c +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "variant.h" +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), @@ -122,8 +122,7 @@ static const struct pad_config gpio_table[] = { /* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c index 4b18e79e29..a259547771 100644 --- a/src/mainboard/siemens/chili/variants/chili/gpio.c +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "variant.h" +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), @@ -121,8 +121,7 @@ static const struct pad_config gpio_table[] = { /* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index ebffc8d39d..3a838240ef 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -3,8 +3,7 @@ #include #include #include - -#include "../../variant.h" +#include void variant_romstage_params(FSPM_UPD *const mupd) { diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index df2ccfaa2e..6298f3b746 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR) += noncar diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc new file mode 100644 index 0000000000..d6b8b52711 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += pre_c.S diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S similarity index 100% rename from src/soc/amd/picasso/bootblock/pre_c.S rename to src/soc/amd/common/block/cpu/noncar/pre_c.S diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 74ea69784d..a59d87eb54 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -1,6 +1,14 @@ config SOC_AMD_COMMON_BLOCK_PCI bool default n + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF help This option builds functions used to program PCI interrupt routing, both PIC and APIC modes. + +config SOC_AMD_COMMON_BLOCK_PCI_MMCONF + bool + default n + help + Selecting this option adds the AMD-common enable_pci_mmconf function + to the build. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 1fed96e45a..78453d464f 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,8 +1,11 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -# FIXME: This gets added when CONFIG_SOC_AMD_COMMON is set, which is a bit unexpected. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) + bootblock-y += amd_pci_mmconf.c verstage_x86-y += amd_pci_mmconf.c romstage-y += amd_pci_mmconf.c postcar-y += amd_pci_mmconf.c ramstage-y += amd_pci_mmconf.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc index aff927a5d0..8a6f1162f8 100644 --- a/src/soc/amd/common/vboot/Makefile.inc +++ b/src/soc/amd/common/vboot/Makefile.inc @@ -4,3 +4,5 @@ verstage-y += vbnv_cmos.c romstage-y += vbnv_cmos.c ramstage-y += vbnv_cmos.c endif + +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c diff --git a/src/soc/amd/picasso/bootblock/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c similarity index 50% rename from src/soc/amd/picasso/bootblock/vboot_bootblock.c rename to src/soc/amd/common/vboot/vboot_bootblock.c index 3fbc4ef608..da652eb8bc 100644 --- a/src/soc/amd/picasso/bootblock/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -2,13 +2,23 @@ #include #include +#include #include #include #include #include #include +#include #include <2struct.h> +static int transfer_buffer_valid(const struct transfer_info_struct *ptr) +{ + if (ptr->magic_val == TRANSFER_MAGIC_VAL) + return 1; + else + return 0; +} + void verify_psp_transfer_buf(void) { if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { @@ -37,7 +47,7 @@ void show_psp_transfer_info(void) struct transfer_info_struct *info = (struct transfer_info_struct *) (void *)(uintptr_t)_transfer_buffer; - if (info->magic_val == TRANSFER_MAGIC_VAL) { + if (transfer_buffer_valid(info)) { if ((info->psp_info & PSP_INFO_VALID) == 0) { printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); return; @@ -51,3 +61,43 @@ void show_psp_transfer_info(void) "Production" : "Pre-Production"); } } + +void boot_with_psp_timestamp(uint64_t base_timestamp) +{ + const struct transfer_info_struct *info = (const struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (!transfer_buffer_valid(info) || info->timestamp == 0) + return; + + /* + * info->timestamp is PSP's timestamp (in microseconds) + * when x86 processor is released. + */ + uint64_t psp_last_ts = info->timestamp; + + int i; + struct timestamp_table *psp_ts_table = + (struct timestamp_table *)(void *) + ((uintptr_t)_transfer_buffer + info->timestamp_offset); + /* new base_timestamp will be offset for all PSP timestamps. */ + base_timestamp -= psp_last_ts; + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * We ignore the time between x86 processor release and bootblock. + * Since timestamp_add subtracts base_time, we first add old base_time + * to make it absolute then add base_timestamp again since + * it'll be a new base_time. + * + * We don't need to convert unit since both PSP and coreboot + * will use 1us granularity. + * + */ + tse->entry_stamp += psp_ts_table->base_time + base_timestamp; + } + + bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, + psp_ts_table->num_entries); +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6fa36641cd..7bcc316218 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -376,12 +376,6 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 150 -config PICASSO_LPC_IOMUX - bool - help - Picasso's LPC bus signals are MUXed with some of the EMMC signals. - Select this option if LPC signals are required. - config DISABLE_SPI_FLASH_ROM_SHARING def_bool n help @@ -406,14 +400,6 @@ config FSP_TEMP_RAM_SIZE menu "PSP Configuration Options" -config AMDFW_OUTSIDE_CBFS - bool - default n - help - The AMDFW (PSP) is typically locatable in cbfs. Select this - option to manually attach the generated amdfw.rom outside of - cbfs. The location is selected by the FWM position. - config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6ec4cd1151..b5e409b055 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,8 +11,7 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/pre_c.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c bootblock-y += i2c.c @@ -24,7 +23,6 @@ bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c -bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 1f7dcb02e4..00f26fe48e 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -21,7 +21,7 @@ * waiting for each device to become available, a single delay will be * executed. The console UART is handled separately from this table. */ -const static int aoac_devs[] = { +const static unsigned int aoac_devs[] = { FCH_AOAC_DEV_AMBA, FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, @@ -45,7 +45,7 @@ void power_off_aoac_device(unsigned int dev) { uint8_t byte; - /* Power on the UART and AMBA devices */ + /* Power off the UART and AMBA devices */ byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte &= ~FCH_AOAC_PWR_ON_DEV; aoac_write8(AOAC_DEV_D3_CTL(dev), byte); diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock.c similarity index 75% rename from src/soc/amd/picasso/bootblock/bootblock.c rename to src/soc/amd/picasso/bootblock.c index 4bff042a91..0b52a17307 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -18,7 +17,6 @@ #include #include #include -#include asmlinkage void bootblock_resume_entry(void); @@ -110,54 +108,6 @@ static void write_resume_eip(void) wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } -static int transfer_buffer_valid(const struct transfer_info_struct *ptr) -{ - if (ptr->magic_val == TRANSFER_MAGIC_VAL) - return 1; - else - return 0; -} - -static void boot_with_psp_timestamp(uint64_t base_timestamp) -{ - const struct transfer_info_struct *info = (const struct transfer_info_struct *) - (void *)(uintptr_t)_transfer_buffer; - - if (!transfer_buffer_valid(info) || info->timestamp == 0) - return; - - /* - * info->timestamp is PSP's timestamp (in microseconds) - * when x86 processor is released. - */ - uint64_t psp_last_ts = info->timestamp; - - int i; - struct timestamp_table *psp_ts_table = - (struct timestamp_table *)(void *) - ((uintptr_t)_transfer_buffer + info->timestamp_offset); - /* new base_timestamp will be offset for all PSP timestamps. */ - base_timestamp -= psp_last_ts; - - for (i = 0; i < psp_ts_table->num_entries; i++) { - struct timestamp_entry *tse = &psp_ts_table->entries[i]; - /* - * We ignore the time between x86 processor release and bootblock. - * Since timestamp_add subtracts base_time, we first add old base_time - * to make it absolute then add base_timestamp again since - * it'll be a new base_time. - * - * We don't need to convert unit since both PSP and coreboot - * will use 1us granularity. - * - */ - tse->entry_stamp += psp_ts_table->base_time + base_timestamp; - } - - bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, - psp_ts_table->num_entries); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index ce197c11e2..8c78496cea 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -46,6 +46,8 @@ _Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE, \ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ +void boot_with_psp_timestamp(uint64_t base_timestamp); #endif diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 311ea6886b..8cdf6ccdbe 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -12,7 +12,7 @@ subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c similarity index 100% rename from src/soc/amd/stoneyridge/bootblock/bootblock.c rename to src/soc/amd/stoneyridge/bootblock.c diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cbd9caad95..9450a92723 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -190,16 +190,20 @@ #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_USB2 18 +#define FCH_AOAC_DEV_USB3 23 + /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -209,16 +213,6 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -292,11 +286,6 @@ void soc_enable_psp_early(void); #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { - int enable; - int status; -}; - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 267f747b4f..05f3072edd 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,14 +31,13 @@ * waiting for each device to become available, a single delay will be * executed. */ -static const struct stoneyridge_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, }; static int is_sata_config(void) @@ -146,21 +145,21 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(unsigned int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -174,14 +173,14 @@ void enable_aoac_devices(void) int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); } while (!status); } @@ -545,14 +544,14 @@ static void set_sb_final_nvs(void) if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc65c1..167342f12e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include #include +.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -161,6 +162,15 @@ car_init_done: /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp /* push TSC value to stack */ @@ -168,6 +178,7 @@ car_init_done: pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_carstage: post_code(0x2A) diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 9480a5a9c6..191232a3b0 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -28,7 +28,11 @@ chipset_teardown_car: * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. */ +#if ENV_X86_64 + pop %rbx +#else pop %ebx +#endif /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx @@ -95,4 +99,8 @@ car_nem_enhanced_teardown: #endif /* Return to caller. */ +#if ENV_X86_64 + jmp *%rbx +#else jmp *%ebx +#endif diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa796..dc32970267 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -304,7 +304,7 @@ static void southbridge_smi_store( reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } @@ -409,7 +409,7 @@ void smihandler_southbridge_pm1( if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - pmc_disable_pm1_control(-1UL); + pmc_disable_pm1_control(~0); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 53d6077e5f..ca11ee612a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -95,8 +95,8 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ada06f217d..3eb72fa57a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -434,7 +434,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) soc_irq_settings(params); } -/* Mainboard GPIO Configuration */ +/* Mainboard FSP Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b755fe1811..d0fbc49a36 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 96737cfbb6..ecfc1e1c5f 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 config ENABLE_IDE_COMBINED_MODE diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 89dcad6086..c87d7a0904 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index adb00e485f..a30dad0cdb 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" diff --git a/util/pgtblgen/Makefile.inc b/util/pgtblgen/Makefile.inc index c4f3ef37b6..08fb6209e5 100644 --- a/util/pgtblgen/Makefile.inc +++ b/util/pgtblgen/Makefile.inc @@ -14,6 +14,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/pagetables: $(PGTBLGEN) $(obj)/config.h $(PGTBLGEN): util/pgtblgen/pgtblgen.c printf " MAKE Creating PGTBLGEN tool\n" - $(HOSTCC) $< -I$(obj) -o $@ + $(HOSTCC) -std=c99 $< -I$(obj) -o $@ endif diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 640d0ba7be..7ed98b2825 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -9,6 +9,7 @@ #include #include #include +#include static void usage(char *argv[]) {