From 21cdf0de086e045988b93b6030f8faa5127f5cdf Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 16:24:29 +0100 Subject: [PATCH 01/44] soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONF Add a Kconfig symbol for including the PCIe MMCONF setup function in the build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the southbridges call enable_pci_mmconf(), but don't select SOC_AMD_COMMON_BLOCK_PCI. Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47878 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/pci/Kconfig | 8 ++++++++ src/soc/amd/common/block/pci/Makefile.inc | 5 ++++- src/southbridge/amd/agesa/hudson/Kconfig | 1 + src/southbridge/amd/cimx/sb800/Kconfig | 1 + src/southbridge/amd/pi/hudson/Kconfig | 1 + 5 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 74ea69784d..a59d87eb54 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -1,6 +1,14 @@ config SOC_AMD_COMMON_BLOCK_PCI bool default n + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF help This option builds functions used to program PCI interrupt routing, both PIC and APIC modes. + +config SOC_AMD_COMMON_BLOCK_PCI_MMCONF + bool + default n + help + Selecting this option adds the AMD-common enable_pci_mmconf function + to the build. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 1fed96e45a..78453d464f 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,8 +1,11 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -# FIXME: This gets added when CONFIG_SOC_AMD_COMMON is set, which is a bit unexpected. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) + bootblock-y += amd_pci_mmconf.c verstage_x86-y += amd_pci_mmconf.c romstage-y += amd_pci_mmconf.c postcar-y += amd_pci_mmconf.c ramstage-y += amd_pci_mmconf.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index b755fe1811..d0fbc49a36 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 96737cfbb6..ecfc1e1c5f 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -10,6 +10,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF if SOUTHBRIDGE_AMD_CIMX_SB800 config ENABLE_IDE_COMBINED_MODE diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 89dcad6086..c87d7a0904 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF config EHCI_BAR hex From 84eb61c32c4ca3f01e17cb4a4e9287821646f5cb Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 16:54:05 +0100 Subject: [PATCH 02/44] soc/amd: move assembly part of non-CAR bootblock to common directory There will be more files added to the common non-CAR Makefile.inc, so use an ifeq statement there. Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/block/cpu/Makefile.inc | 1 + src/soc/amd/common/block/cpu/noncar/Makefile.inc | 1 + .../amd/{picasso/bootblock => common/block/cpu/noncar}/pre_c.S | 0 src/soc/amd/picasso/Makefile.inc | 1 - 4 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 src/soc/amd/common/block/cpu/noncar/Makefile.inc rename src/soc/amd/{picasso/bootblock => common/block/cpu/noncar}/pre_c.S (100%) diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index df2ccfaa2e..6298f3b746 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR) += noncar diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc new file mode 100644 index 0000000000..d6b8b52711 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += pre_c.S diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S similarity index 100% rename from src/soc/amd/picasso/bootblock/pre_c.S rename to src/soc/amd/common/block/cpu/noncar/pre_c.S diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6ec4cd1151..5f4ab9bddb 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/pre_c.S bootblock-y += bootblock/bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c From 9900c4f0b041cb0ac1c958500453a803beda3c8c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Nov 2020 18:02:39 +0100 Subject: [PATCH 03/44] soc/amd: move vboot bootblock functions to common folder Change-Id: I9e9fed26a686b8f90797687dd720902be48dae72 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/vboot/Makefile.inc | 2 ++ .../amd/{picasso/bootblock => common/vboot}/vboot_bootblock.c | 0 src/soc/amd/picasso/Makefile.inc | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) rename src/soc/amd/{picasso/bootblock => common/vboot}/vboot_bootblock.c (100%) diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc index aff927a5d0..8a6f1162f8 100644 --- a/src/soc/amd/common/vboot/Makefile.inc +++ b/src/soc/amd/common/vboot/Makefile.inc @@ -4,3 +4,5 @@ verstage-y += vbnv_cmos.c romstage-y += vbnv_cmos.c ramstage-y += vbnv_cmos.c endif + +bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += vboot_bootblock.c diff --git a/src/soc/amd/picasso/bootblock/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c similarity index 100% rename from src/soc/amd/picasso/bootblock/vboot_bootblock.c rename to src/soc/amd/common/vboot/vboot_bootblock.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5f4ab9bddb..f010c7b055 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -23,7 +23,6 @@ bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c bootblock-y += reset.c -bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c From cd50715e0334fb16006788506e3815e489d337a9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Nov 2020 20:37:15 +0100 Subject: [PATCH 04/44] soc/amd: move vboot-on-PSP-related functions to common/vboot Change-Id: I4f07d3ab12116229a13d2e8c02b2deb06e51a1af Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/vboot/vboot_bootblock.c | 50 +++++++++++++++++++ src/soc/amd/picasso/bootblock/bootblock.c | 50 ------------------- .../amd/picasso/include/soc/psp_transfer.h | 2 + 3 files changed, 52 insertions(+), 50 deletions(-) diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 3fbc4ef608..45ad9de03e 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -2,13 +2,23 @@ #include #include +#include #include #include #include #include #include +#include #include <2struct.h> +static int transfer_buffer_valid(const struct transfer_info_struct *ptr) +{ + if (ptr->magic_val == TRANSFER_MAGIC_VAL) + return 1; + else + return 0; +} + void verify_psp_transfer_buf(void) { if (*(uint32_t *)_vboot2_work == VB2_SHARED_DATA_MAGIC) { @@ -51,3 +61,43 @@ void show_psp_transfer_info(void) "Production" : "Pre-Production"); } } + +void boot_with_psp_timestamp(uint64_t base_timestamp) +{ + const struct transfer_info_struct *info = (const struct transfer_info_struct *) + (void *)(uintptr_t)_transfer_buffer; + + if (!transfer_buffer_valid(info) || info->timestamp == 0) + return; + + /* + * info->timestamp is PSP's timestamp (in microseconds) + * when x86 processor is released. + */ + uint64_t psp_last_ts = info->timestamp; + + int i; + struct timestamp_table *psp_ts_table = + (struct timestamp_table *)(void *) + ((uintptr_t)_transfer_buffer + info->timestamp_offset); + /* new base_timestamp will be offset for all PSP timestamps. */ + base_timestamp -= psp_last_ts; + + for (i = 0; i < psp_ts_table->num_entries; i++) { + struct timestamp_entry *tse = &psp_ts_table->entries[i]; + /* + * We ignore the time between x86 processor release and bootblock. + * Since timestamp_add subtracts base_time, we first add old base_time + * to make it absolute then add base_timestamp again since + * it'll be a new base_time. + * + * We don't need to convert unit since both PSP and coreboot + * will use 1us granularity. + * + */ + tse->entry_stamp += psp_ts_table->base_time + base_timestamp; + } + + bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, + psp_ts_table->num_entries); +} diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 4bff042a91..0b52a17307 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -18,7 +17,6 @@ #include #include #include -#include asmlinkage void bootblock_resume_entry(void); @@ -110,54 +108,6 @@ static void write_resume_eip(void) wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); } -static int transfer_buffer_valid(const struct transfer_info_struct *ptr) -{ - if (ptr->magic_val == TRANSFER_MAGIC_VAL) - return 1; - else - return 0; -} - -static void boot_with_psp_timestamp(uint64_t base_timestamp) -{ - const struct transfer_info_struct *info = (const struct transfer_info_struct *) - (void *)(uintptr_t)_transfer_buffer; - - if (!transfer_buffer_valid(info) || info->timestamp == 0) - return; - - /* - * info->timestamp is PSP's timestamp (in microseconds) - * when x86 processor is released. - */ - uint64_t psp_last_ts = info->timestamp; - - int i; - struct timestamp_table *psp_ts_table = - (struct timestamp_table *)(void *) - ((uintptr_t)_transfer_buffer + info->timestamp_offset); - /* new base_timestamp will be offset for all PSP timestamps. */ - base_timestamp -= psp_last_ts; - - for (i = 0; i < psp_ts_table->num_entries; i++) { - struct timestamp_entry *tse = &psp_ts_table->entries[i]; - /* - * We ignore the time between x86 processor release and bootblock. - * Since timestamp_add subtracts base_time, we first add old base_time - * to make it absolute then add base_timestamp again since - * it'll be a new base_time. - * - * We don't need to convert unit since both PSP and coreboot - * will use 1us granularity. - * - */ - tse->entry_stamp += psp_ts_table->base_time + base_timestamp; - } - - bootblock_main_with_timestamp(base_timestamp, psp_ts_table->entries, - psp_ts_table->num_entries); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index ce197c11e2..8c78496cea 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -46,6 +46,8 @@ _Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE, \ void verify_psp_transfer_buf(void); /* Display the transfer block's PSP_info data */ void show_psp_transfer_info(void); +/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */ +void boot_with_psp_timestamp(uint64_t base_timestamp); #endif From 3e22cb6e1c72c5d277e760db3fd56de663715083 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Nov 2020 20:51:54 +0100 Subject: [PATCH 05/44] soc/amd/common/vboot: use transfer_buffer_valid function show_psp_transfer_info reimplemented the functionality of transfer_buffer_valid, so use replace that with a function call. Change-Id: Ie3d373b10bdb0ab00640dabeea12b13ec25406cc Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47977 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/vboot/vboot_bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 45ad9de03e..da652eb8bc 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -47,7 +47,7 @@ void show_psp_transfer_info(void) struct transfer_info_struct *info = (struct transfer_info_struct *) (void *)(uintptr_t)_transfer_buffer; - if (info->magic_val == TRANSFER_MAGIC_VAL) { + if (transfer_buffer_valid(info)) { if ((info->psp_info & PSP_INFO_VALID) == 0) { printk(BIOS_INFO, "No PSP info found in transfer buffer.\n"); return; From de2ba63f479bdeb7721310fdb9aa7e46c4eeffac Mon Sep 17 00:00:00 2001 From: Frank Chu Date: Fri, 20 Nov 2020 14:59:27 +0800 Subject: [PATCH 06/44] mb/google/volteer: Create drobit variant Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/Kconfig | 2 ++ src/mainboard/google/volteer/Kconfig.name | 4 ++++ .../volteer/variants/drobit/include/variant/ec.h | 8 ++++++++ .../variants/drobit/include/variant/gpio.h | 15 +++++++++++++++ .../volteer/variants/drobit/memory/Makefile.inc | 5 +++++ .../variants/drobit/memory/dram_id.generated.txt | 1 + .../variants/drobit/memory/mem_parts_used.txt | 4 ++++ .../volteer/variants/drobit/overridetree.cb | 6 ++++++ 8 files changed, 45 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/drobit/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h create mode 100644 src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/volteer/variants/drobit/overridetree.cb diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 1553a3af54..f2e4adc1cc 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -106,6 +106,7 @@ config MAINBOARD_PART_NUMBER default "Boldar" if BOARD_GOOGLE_BOLDAR default "Elemi" if BOARD_GOOGLE_ELEMI default "Voema" if BOARD_GOOGLE_VOEMA + default "Drobit" if BOARD_GOOGLE_DROBIT config MAX_CPUS int @@ -146,6 +147,7 @@ config VARIANT_DIR default "boldar" if BOARD_GOOGLE_BOLDAR default "elemi" if BOARD_GOOGLE_ELEMI default "voema" if BOARD_GOOGLE_VOEMA + default "drobit" if BOARD_GOOGLE_DROBIT config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 0f9b6e287c..7536dc5eb1 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -89,3 +89,7 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + +config BOARD_GOOGLE_DROBIT + bool "-> Drobit" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h new file mode 100644 index 0000000000..b5fa8c5485 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt new file mode 100644 index 0000000000..f51b3af398 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt @@ -0,0 +1,4 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb new file mode 100644 index 0000000000..32204c58e7 --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end From 0aada3cddb37e6f854420a06b565c7db64360650 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Nov 2020 22:55:53 +0100 Subject: [PATCH 07/44] soc/amd: move bootblock inside main SoC directories There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory to avoid clutter. This makes soc/amd more consistent with the coreboot code base in src/northbridge, src/southbridge and src/soc with the exception of src/soc/intel. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982 Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 2 +- src/soc/amd/picasso/{bootblock => }/bootblock.c | 0 src/soc/amd/stoneyridge/Makefile.inc | 2 +- src/soc/amd/stoneyridge/{bootblock => }/bootblock.c | 0 4 files changed, 2 insertions(+), 2 deletions(-) rename src/soc/amd/picasso/{bootblock => }/bootblock.c (100%) rename src/soc/amd/stoneyridge/{bootblock => }/bootblock.c (100%) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f010c7b055..b5e409b055 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -11,7 +11,7 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += aoac.c bootblock-y += southbridge.c bootblock-y += i2c.c diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock.c similarity index 100% rename from src/soc/amd/picasso/bootblock/bootblock.c rename to src/soc/amd/picasso/bootblock.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 311ea6886b..8cdf6ccdbe 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -12,7 +12,7 @@ subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c bootblock-y += BiosCallOuts.c -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c similarity index 100% rename from src/soc/amd/stoneyridge/bootblock/bootblock.c rename to src/soc/amd/stoneyridge/bootblock.c From ffb4652461b4ee8da2b816c5288c3076b7379de4 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 22:49:36 +0100 Subject: [PATCH 08/44] soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig option The corresponding functionality in the SoC's Makefile.inc was removed in commit ef3395d990bbf1118a8d4e367a986bdbc92b1820 Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/Kconfig | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6fa36641cd..c3995c87c7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -406,14 +406,6 @@ config FSP_TEMP_RAM_SIZE menu "PSP Configuration Options" -config AMDFW_OUTSIDE_CBFS - bool - default n - help - The AMDFW (PSP) is typically locatable in cbfs. Select this - option to manually attach the generated amdfw.rom outside of - cbfs. The location is selected by the FWM position. - config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 From e2cb8696f0ea1522b256bcb3973c659c3cd76384 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 23:01:45 +0100 Subject: [PATCH 09/44] soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoC PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/amd/mandolin/Kconfig | 4 ++-- src/mainboard/amd/mandolin/Makefile.inc | 2 +- src/mainboard/amd/mandolin/mainboard.c | 4 ++-- src/soc/amd/picasso/Kconfig | 6 ------ 4 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index b779630d56..67766217e8 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -21,7 +21,7 @@ config FMDFILE config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" default n - select PICASSO_LPC_IOMUX + select MANDOLIN_LPC select SUPERIO_SMSC_SIO1036 help AMD's debug card contains an SMSC SIO1036 device which provides an @@ -111,7 +111,7 @@ config MANDOLIN_IOMUX_USE_EMMC endchoice endif # !AMD_LPC_DEBUG_CARD -config PICASSO_LPC_IOMUX +config MANDOLIN_LPC bool default y if MANDOLIN_IOMUX_USE_LPC help diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index 778701834f..795a28fde2 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -6,7 +6,7 @@ bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c -ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) +ifneq ($(CONFIG_MANDOLIN_LPC),y) ramstage-y += emmc_gpio.c endif diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c index 247616cff7..b509282f8b 100644 --- a/src/mainboard/amd/mandolin/mainboard.c +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -111,13 +111,13 @@ static void mainboard_init(void *chip_info) { struct soc_amd_picasso_config *cfg = config_of_soc(); - if (!CONFIG(PICASSO_LPC_IOMUX)) + if (!CONFIG(MANDOLIN_LPC)) cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; mainboard_program_gpios(); /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ - if (CONFIG(PICASSO_LPC_IOMUX)) + if (CONFIG(MANDOLIN_LPC)) printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); else mainboard_program_emmc_gpios(); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index c3995c87c7..7bcc316218 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -376,12 +376,6 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 150 -config PICASSO_LPC_IOMUX - bool - help - Picasso's LPC bus signals are MUXed with some of the EMMC signals. - Select this option if LPC signals are required. - config DISABLE_SPI_FLASH_ROM_SHARING def_bool n help From 36c2ea4a630fee8607599baab7d8a9dcd2f9ca53 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 25 Nov 2020 16:24:05 +0000 Subject: [PATCH 10/44] util/pgtblgen: Improve compatibility Fix build on Debian/jessie Change-Id: I987e7a03441b40ab06ccd54a21e38aac81a1c28d Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/48004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- util/pgtblgen/Makefile.inc | 2 +- util/pgtblgen/pgtblgen.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/util/pgtblgen/Makefile.inc b/util/pgtblgen/Makefile.inc index c4f3ef37b6..08fb6209e5 100644 --- a/util/pgtblgen/Makefile.inc +++ b/util/pgtblgen/Makefile.inc @@ -14,6 +14,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/pagetables: $(PGTBLGEN) $(obj)/config.h $(PGTBLGEN): util/pgtblgen/pgtblgen.c printf " MAKE Creating PGTBLGEN tool\n" - $(HOSTCC) $< -I$(obj) -o $@ + $(HOSTCC) -std=c99 $< -I$(obj) -o $@ endif diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 640d0ba7be..7ed98b2825 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -9,6 +9,7 @@ #include #include #include +#include static void usage(char *argv[]) { From 3616e9c3b0806bd7f6a1960b658faec635d20dc4 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 25 Nov 2020 20:10:49 +0000 Subject: [PATCH 11/44] soc/intel/skylake: Fix comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mainboard_silicon_init_params() is *not* meant for configuring GPIOs. It should only be used to configure FSP options, which can not be configured elsewhere. Change-Id: Ia92d0d173af9c67600e93b473480967304772998 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/48008 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ada06f217d..3eb72fa57a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -434,7 +434,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) soc_irq_settings(params); } -/* Mainboard GPIO Configuration */ +/* Mainboard FSP Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); From 48b80c134a1c5c3574e73104d6bfd13481568a70 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sun, 22 Nov 2020 17:18:30 +0000 Subject: [PATCH 12/44] mb/kontron/bsl6: Configure GPIOs using mainboard_ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/kontron/bsl6/ramstage.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index 19518f74a4..771c6aae7b 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; From e8774933d39fab2cb4eb443f69a583d1fa5bd238 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 24 Nov 2020 19:27:47 +0000 Subject: [PATCH 13/44] mb/siemens/chili: Introduce include folder for header files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use include folder for header files allowing proper includes. Change-Id: I80066fb925b918d040062397e633c5d499a50dbe Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47973 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/siemens/chili/Makefile.inc | 2 +- src/mainboard/siemens/chili/ec.c | 3 +-- src/mainboard/siemens/chili/{ => include/mainboard}/ec.h | 0 src/mainboard/siemens/chili/{ => include}/variant.h | 0 src/mainboard/siemens/chili/mainboard.c | 3 +-- src/mainboard/siemens/chili/romstage.c | 3 +-- src/mainboard/siemens/chili/variants/base/gpio.c | 2 +- src/mainboard/siemens/chili/variants/chili/gpio.c | 2 +- src/mainboard/siemens/chili/variants/chili/romstage.c | 3 +-- 9 files changed, 7 insertions(+), 11 deletions(-) rename src/mainboard/siemens/chili/{ => include/mainboard}/ec.h (100%) rename src/mainboard/siemens/chili/{ => include}/variant.h (100%) diff --git a/src/mainboard/siemens/chili/Makefile.inc b/src/mainboard/siemens/chili/Makefile.inc index abeedf3a85..c57c0a50dc 100644 --- a/src/mainboard/siemens/chili/Makefile.inc +++ b/src/mainboard/siemens/chili/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include romstage-y += romstage.c diff --git a/src/mainboard/siemens/chili/ec.c b/src/mainboard/siemens/chili/ec.c index bc0eb7d9ff..7d9b6f2495 100644 --- a/src/mainboard/siemens/chili/ec.c +++ b/src/mainboard/siemens/chili/ec.c @@ -4,10 +4,9 @@ #include #include #include +#include #include -#include "ec.h" - #define EC_STATUS 0x50 #define EC_RUNNING (1 << 1) #define EC_DEVICE_CONTROL_1 0x80 diff --git a/src/mainboard/siemens/chili/ec.h b/src/mainboard/siemens/chili/include/mainboard/ec.h similarity index 100% rename from src/mainboard/siemens/chili/ec.h rename to src/mainboard/siemens/chili/include/mainboard/ec.h diff --git a/src/mainboard/siemens/chili/variant.h b/src/mainboard/siemens/chili/include/variant.h similarity index 100% rename from src/mainboard/siemens/chili/variant.h rename to src/mainboard/siemens/chili/include/variant.h diff --git a/src/mainboard/siemens/chili/mainboard.c b/src/mainboard/siemens/chili/mainboard.c index 91395eac07..c1d1a1d941 100644 --- a/src/mainboard/siemens/chili/mainboard.c +++ b/src/mainboard/siemens/chili/mainboard.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include - -#include "ec.h" +#include static void mainboard_dev_init(struct device *dev) { diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index c1ec7e4982..a981f50a7b 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -4,8 +4,7 @@ #include #include #include - -#include "variant.h" +#include static void mainboard_init(void) { diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c index 65ea037a3a..61ec27dfa6 100644 --- a/src/mainboard/siemens/chili/variants/base/gpio.c +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "variant.h" +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c index 4b18e79e29..d7e5ab02b2 100644 --- a/src/mainboard/siemens/chili/variants/chili/gpio.c +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include "variant.h" +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), diff --git a/src/mainboard/siemens/chili/variants/chili/romstage.c b/src/mainboard/siemens/chili/variants/chili/romstage.c index ebffc8d39d..3a838240ef 100644 --- a/src/mainboard/siemens/chili/variants/chili/romstage.c +++ b/src/mainboard/siemens/chili/variants/chili/romstage.c @@ -3,8 +3,7 @@ #include #include #include - -#include "../../variant.h" +#include void variant_romstage_params(FSPM_UPD *const mupd) { From 617150e0ff5b84b531e88e89d5ab7d3f93636434 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Tue, 24 Nov 2020 19:48:36 +0000 Subject: [PATCH 14/44] mb/siemens/chili: Configure GPIOs in gpio.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead of passing data around. Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/siemens/chili/include/mainboard/gpio.h | 8 ++++++++ src/mainboard/siemens/chili/include/variant.h | 2 -- src/mainboard/siemens/chili/romstage.c | 12 ++---------- src/mainboard/siemens/chili/variants/base/gpio.c | 7 +++---- src/mainboard/siemens/chili/variants/chili/gpio.c | 7 +++---- 5 files changed, 16 insertions(+), 20 deletions(-) create mode 100644 src/mainboard/siemens/chili/include/mainboard/gpio.h diff --git a/src/mainboard/siemens/chili/include/mainboard/gpio.h b/src/mainboard/siemens/chili/include/mainboard/gpio.h new file mode 100644 index 0000000000..ef2a21c418 --- /dev/null +++ b/src/mainboard/siemens/chili/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/siemens/chili/include/variant.h b/src/mainboard/siemens/chili/include/variant.h index 2bbe7d7926..1d97728513 100644 --- a/src/mainboard/siemens/chili/include/variant.h +++ b/src/mainboard/siemens/chili/include/variant.h @@ -7,6 +7,4 @@ void variant_romstage_params(FSPM_UPD *); -const struct pad_config *variant_gpio_table(size_t *num); - #endif /* _VARIANT_H_ */ diff --git a/src/mainboard/siemens/chili/romstage.c b/src/mainboard/siemens/chili/romstage.c index a981f50a7b..7453fa58e4 100644 --- a/src/mainboard/siemens/chili/romstage.c +++ b/src/mainboard/siemens/chili/romstage.c @@ -1,20 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include -static void mainboard_init(void) -{ - const struct pad_config *pads; - size_t num; - - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { uint8_t vtd = 1; @@ -39,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) variant_romstage_params(memupd); - mainboard_init(); + mainboard_configure_gpios(); } __weak void variant_romstage_params(FSPM_UPD *const mupd) diff --git a/src/mainboard/siemens/chili/variants/base/gpio.c b/src/mainboard/siemens/chili/variants/base/gpio.c index 61ec27dfa6..9d459ccc2a 100644 --- a/src/mainboard/siemens/chili/variants/base/gpio.c +++ b/src/mainboard/siemens/chili/variants/base/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO */ PAD_NC(GPP_A14, NONE), @@ -122,8 +122,7 @@ static const struct pad_config gpio_table[] = { /* GPP_J11 A4WP_PRESENT */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/siemens/chili/variants/chili/gpio.c b/src/mainboard/siemens/chili/variants/chili/gpio.c index d7e5ab02b2..a259547771 100644 --- a/src/mainboard/siemens/chili/variants/chili/gpio.c +++ b/src/mainboard/siemens/chili/variants/chili/gpio.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include static const struct pad_config gpio_table[] = { /* GPP_A14 GPIO 0x0000002644000300 */ PAD_NC(GPP_A14, NONE), @@ -121,8 +121,7 @@ static const struct pad_config gpio_table[] = { /* GPP_J11 A4WP_PRESENT 0x0000003944000700 */ PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), }; -const struct pad_config *variant_gpio_table(size_t *num) +void mainboard_configure_gpios(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } From 679b236bedd42d4a97a15d108b605ae8d4e5ee9a Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Fri, 27 Nov 2020 12:11:33 -0700 Subject: [PATCH 15/44] util/mb/google/puff: remove HECI from overridetree The template for overridetree.cb includes HeciEnabled, which has been removed from the CNL config struct, so remove it from the overridetree. BUG=b:174360951 TEST=`new_variant_fulltest.sh puff` succeeds Signed-off-by: Paul Fagerburg Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48129 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- util/mainboard/google/puff/template/overridetree.cb | 3 --- 1 file changed, 3 deletions(-) diff --git a/util/mainboard/google/puff/template/overridetree.cb b/util/mainboard/google/puff/template/overridetree.cb index adb00e485f..a30dad0cdb 100644 --- a/util/mainboard/google/puff/template/overridetree.cb +++ b/util/mainboard/google/puff/template/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" From 3c729487bf2de44c15d0c3541ff97ed16511b635 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 24 Nov 2020 17:56:37 +0800 Subject: [PATCH 16/44] Makefile.inc: Alloc .bss* sections for "struct" file type When the global variable of a "struct" CBFS file is zero (for example, CB:47696), the binary will appear in the .bss* section in the ELF file (instead of .data). This results in an empty binary file added to CBFS, so that file size check will fail when reading it at runtime. BUG=b:173751635 TEST=emerge-asurada coreboot TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS BRANCH=none Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47903 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index fafb9ecd0d..95846a75c7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -338,7 +338,7 @@ cbfs-files-processor-struct= \ $(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \ printf " CC+STRIP $(@)\n"; \ $(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \ - $(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \ + $(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \ rm -f $(2).tmp) \ $(eval DEPENDENCIES += $(2).d) From 4cb8776c31ceb4a5b9e353b2e9b2a4f751e1dc54 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 27 Nov 2020 00:16:46 +0530 Subject: [PATCH 17/44] mb/intel/adlrvp: Refactor lpddr4_mem_config structure List of changes: 1. Initialize dq_map array in a single line 2. Make dqs_map array also in a single line TEST=Able to build and boot ADLRVP LP4 SKU. Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077 Reviewed-by: Angel Pons Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/memory.c | 28 +++++++++------------------- 1 file changed, 9 insertions(+), 19 deletions(-) diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 5d374db2a6..b203f69240 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -22,29 +22,19 @@ static const struct mb_cfg ddr4_mem_config = { static const struct mb_cfg lpddr4_mem_config = { /* DQ byte map */ .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ - 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ - { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ - 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ - { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ - 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ - { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ - 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ - { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ - 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ - { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ - 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ - { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ - 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ - { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ - 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, + { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, + { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, + { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, + { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, + { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, + { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, + { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, }, /* DQS CPU<>DRAM map */ .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } }, .dq_pins_interleaved = false, From ae81d59ecaf050f7e14adb136560e993a98164cf Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 28 Oct 2020 22:28:07 +0530 Subject: [PATCH 18/44] mb/intel/adlrvp: Add support for LPDDR5 This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: V Sowmya --- .../intel/adlrvp/include/baseboard/variants.h | 2 ++ src/mainboard/intel/adlrvp/memory.c | 30 +++++++++++++++++ .../intel/adlrvp/romstage_fsp_params.c | 5 +-- src/mainboard/intel/adlrvp/spd/Makefile.inc | 6 ++-- .../intel/adlrvp/spd/adlrvp_lp5.spd.hex | 32 +++++++++++++++++++ 5 files changed, 71 insertions(+), 4 deletions(-) create mode 100644 src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 537e62451a..9cb8640860 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -14,6 +14,8 @@ enum adl_boardid { ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5 = 0x13, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index b203f69240..80ec14aa17 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -44,6 +44,34 @@ static const struct mb_cfg lpddr4_mem_config = { .UserBd = BOARD_TYPE_MOBILE, }; +static const struct mb_cfg lp5_mem_config = { + + /* DQ byte map */ + .dq_map = { + { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, + { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, + { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, + { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, + { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, + { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, + { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, + { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = false, /* Early Command Training */ + + .lp5_ccc_config = 0xff, + + .UserBd = BOARD_TYPE_MOBILE, +}; + static const struct mb_cfg ddr5_mem_config = { /* Baseboard uses only 100ohm Rcomp resistors */ .rcomp_resistor = {100, 100, 100}, @@ -71,6 +99,8 @@ const struct mb_cfg *variant_memory_params(void) return &ddr4_mem_config; case ADL_P_DDR5: return &ddr5_mem_config; + case ADL_P_LP5: + return &lp5_mem_config; default: die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 672c59743e..2f03cb4e84 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lpddr4_spd_info = { + const struct spd_info lp4_lp5_spd_info = { .read_type = READ_SPD_CBFS, .spd_spec.spd_index = get_spd_index(), }; @@ -56,7 +56,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) break; case ADL_P_LP4_1: case ADL_P_LP4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + case ADL_P_LP5: + memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc index 1218a76690..10ce42ef4c 100644 --- a/src/mainboard/intel/adlrvp/spd/Makefile.inc +++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc @@ -1,4 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = adlrvp_lp4 #0b000 -SPD_SOURCES += empty # 0b001 +SPD_SOURCES = adlrvp_lp4 # 0b000 +SPD_SOURCES += empty # 0b001 +SPD_SOURCES += empty # 0b002 +SPD_SOURCES += adlrvp_lp5 # 0b003 diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex new file mode 100644 index 0000000000..2f2a31a33d --- /dev/null +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00 +48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 0f044a50074d50dea18a73ffd2683b3860c205e2 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 27 Nov 2020 00:34:52 +0530 Subject: [PATCH 19/44] mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte) TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex index 17f270d0ec..e1d338edbc 100644 --- a/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex +++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp4.spd.hex @@ -1,11 +1,11 @@ -23 12 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 -48 00 04 00 D2 54 01 00 87 40 90 A8 90 C0 08 60 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 01 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 E4 00 60 A1 AC +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 From 840679d2c1d2d17e10866ae412332bb1a8a417b7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 27 Nov 2020 00:46:18 +0530 Subject: [PATCH 20/44] mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Apply W/A to get card detected on x1 slot - Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIe SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080 Reviewed-by: Angel Pons Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/devicetree.cb | 8 +++++++- src/mainboard/intel/adlrvp/gpio.c | 4 ++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 80edb92003..f2f768a8be 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,6 +51,12 @@ chip soc/intel/alderlake register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" + # Enable PCH PCIE RP 8 using free running CLK (0x80) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieRpClkReqDetect[7]" = "1" + # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" @@ -245,7 +251,7 @@ chip soc/intel/alderlake device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 + device pci 1c.7 on end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 on end # RP11 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 89e6f5826b..4cb8c3a06c 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -72,6 +72,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), From 1ce5f5827d95e6fe00e9a3681f3679e44cbb7d47 Mon Sep 17 00:00:00 2001 From: Varshit Pandya Date: Thu, 12 Nov 2020 12:40:36 +0530 Subject: [PATCH 21/44] mb/intel/adlrvp: Update GPIO configuration as per schematics Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics. Signed-off-by: Varshit Pandya Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/gpio.c | 44 +++++++++---------------------- 1 file changed, 12 insertions(+), 32 deletions(-) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 4cb8c3a06c..9b94cec4bd 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -138,22 +138,16 @@ static const struct pad_config gpio_table[] = { /* SPI_MOSI(2) */ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* SPI_MIS0(1) */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* SPI_MIS0(2) */ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* SPI_CLK(1) */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* SPI_CLK(2) */ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* SPI_CS(0, 1) */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPI_CS(1, 0) */ @@ -162,34 +156,26 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ + /* I2C_SCL(1) */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ + /* I2C_SDA(1) */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* I2S0_SCLK */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), @@ -255,10 +241,6 @@ static const struct pad_config gpio_table[] = { /* USB2 OC0 pins */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* USB2 OC1 pins */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* USB2 OC2 pins */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB2 OC3 pins */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), @@ -267,8 +249,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), From e9695f0d70c599ceaf249067e8e3aed716f8a464 Mon Sep 17 00:00:00 2001 From: Varshit Pandya Date: Thu, 12 Nov 2020 13:13:05 +0530 Subject: [PATCH 22/44] mb/intel/adlrvp: Configure Camera related GPIO as per schematics Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496 Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/gpio.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 9b94cec4bd..8ff6fcdbe3 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -26,8 +26,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* M.2 SSD_2 Reset */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM1-IRQ */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* CAM_STROBE */ PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* Audio Codec INT N */ @@ -77,6 +75,14 @@ static const struct pad_config gpio_table[] = { /* SRCCLK_OEB6 */ PAD_CFG_GPO(GPP_E5, 0, PLTRST), + /* CAM1_RST */ + PAD_CFG_GPO(GPP_R5, 1, PLTRST), + /* CAM2_RST */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + /* CAM1_PWR_EN */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM2_PWR_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* THC0 SPI1 CLK */ @@ -186,15 +192,6 @@ static const struct pad_config gpio_table[] = { /* I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S1_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* I2S1_RXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - /* I2S2_SCLK */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SFRM */ From 5e1d4dd94782194fbd7fde6e4e0286ca1f054b37 Mon Sep 17 00:00:00 2001 From: Varshit Pandya Date: Thu, 12 Nov 2020 13:31:42 +0530 Subject: [PATCH 23/44] mb/intel/adlrvp: Add ASL support for WFC annd UFC 1. Add 2 ports and 2 endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 BUG=None BRANCH=None TEST=Build and Boot adlrvp board and able to capture image using camera. Signed-off-by: Varshit Pandya Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497 Reviewed-by: V Sowmya Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../intel/adlrvp/acpi/mipi_camera.asl | 499 ++++++++++++++++++ src/mainboard/intel/adlrvp/dsdt.asl | 3 + 2 files changed, 502 insertions(+) create mode 100644 src/mainboard/intel/adlrvp/acpi/mipi_camera.asl diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl new file mode 100644 index 0000000000..b8bd6dcd9b --- /dev/null +++ b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl @@ -0,0 +1,499 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + One + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} + +Scope (\_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C1.CAM0, + Zero, + Zero + } + } + } + }) +} + +Scope (\_SB.PCI0.I2C1) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(0,1) /* Clock 0, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_B23) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_R5) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_R5) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(0) /* Clock 0 */ + /* Pull RST low */ + CTXS(GPP_R5) + /* Pull PWREN low */ + CTXS(GPP_B23) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM0) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x02) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + Package (0x02) + { + "lens-focus", + Package (0x01) + { + VCM0 + } + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, 0x03) /* _UID: Unique ID */ + Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C1", + 0x00, ResourceConsumer, , + ) + }) + Name (_DEP, Package (0x01) /* _DEP: Dependencies */ + { + CAM0 + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + RCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + RCPR + }) + Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "compatible", + "dongwoon,dw9714" + } + } + }) + } +} + +Scope (\_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ + { + If ((STA == Zero)) + { + /* Enable IMG_CLK */ + MCON(1,1) /* Clock 1, 19.2MHz */ + /* Pull PWREN high */ + STXS(GPP_E16) + Sleep(2) /* reset pulse width */ + /* Pull RST low */ + CTXS(GPP_E15) + Sleep(1) /* t2 */ + /* Pull RST high */ + STXS(GPP_E15) + Sleep(1) /* t2 */ + Store(1,STA) + } + } + Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ + { + If ((STA == One)) + { + /* Disable IMG_CLK */ + Sleep(1) /* t0+t1 */ + MCOF(1) /* Clock 1 */ + /* Pull RST low */ + CTXS(GPP_E15) + /* Pull PWREN low */ + CTXS(GPP_E16) + Store(0,STA) + } + } + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (STA) + } + } + Device (CAM1) + { + Name (_HID, "OVTI5675") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ + { + FCPR + }) + Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ + { + FCPR + }) + Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x05) + { + Package (0x02) + { + "endpoint", + Zero + }, + Package (0x02) + { + "clock-lanes", + Zero + }, + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02 + } + }, + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x1AD27480 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index d4fb7a4273..6e7ccd1d7c 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -27,6 +27,9 @@ DefinitionBlock( #include } + /* Camera */ + #include + #if CONFIG(CHROMEOS) /* Chrome OS specific */ #include From 52fabb12470954b9af414f9c380b36648069c07b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 29 Nov 2020 20:44:45 +0530 Subject: [PATCH 24/44] mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/include/baseboard/ec.h | 3 --- src/mainboard/intel/adlrvp/include/baseboard/gpio.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h index 4303faf0d2..c01829936d 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/ec.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -56,9 +56,6 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h index b61276c0c1..de0adf6cff 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -12,7 +12,4 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* EC sync IRQ */ -#define EC_SYNC_IRQ GPP_A15_IRQ - #endif /* __BASEBOARD_GPIO_H__ */ From f5c3e29bdfd3785db4fb293b0a4873e857eabcb7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 30 Nov 2020 16:10:34 +0530 Subject: [PATCH 25/44] ec/google/chromeec/acpi: Make OperationRegion brace align Inject TAB to make OperationRegion closing brace align with opening brace. Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/acpi/ec.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index d12274f8c0..ce2455f30b 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -82,7 +82,7 @@ Device (EC0) Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power -} + } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) OperationRegion (EMEM, EmbeddedControl, From 39ea2232498fe80cabff0a67d6d3f7dccd964ea0 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Mon, 23 Nov 2020 21:24:20 -0800 Subject: [PATCH 26/44] mb/ocp/deltalake: Update SMBIOS type 8 information Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons --- src/mainboard/ocp/deltalake/ramstage.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 96b006020b..72a74daecc 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -180,6 +180,30 @@ static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) } } +static const struct port_information smbios_type8_info[] = { + { + .internal_reference_designator = "JCN18 - CPU MIPI60", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN32 - TPM_CONN", + .internal_connector_type = CONN_OTHER, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_OTHER_PORT + }, + { + .internal_reference_designator = "JCN7 - USB type C", + .internal_connector_type = CONN_USB_TYPE_C, + .external_reference_designator = "", + .external_connector_type = CONN_NONE, + .port_type = TYPE_USB + }, +}; + static int create_smbios_type9(int *handle, unsigned long *current) { int index; @@ -281,6 +305,13 @@ static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long { int len = 0; + // add port information + len += smbios_write_type8( + current, handle, + smbios_type8_info, + ARRAY_SIZE(smbios_type8_info) + ); + len += create_smbios_type9(handle, current); return len; From 3c02ed9cb6ff664eba31291e36405672529d4103 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 30 Nov 2020 06:56:08 +0100 Subject: [PATCH 27/44] MAINTAINERS: Add missing trailing slashes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing trailing slashes so that Gerrit recognizes maintainers correctly. Signed-off-by: Felix Singer Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48137 Reviewed-by: Michael Niewöhner Reviewed-by: Felix Held Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- MAINTAINERS | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4f643b2f3c..880c4aa445 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,19 +233,19 @@ F: src/mainboard/facebook/monolith/ GETAC P470 MAINBOARD M: Patrick Georgi S: Maintained -F: src/mainboard/getac/p470 +F: src/mainboard/getac/p470/ GIGABYTE GA-G41M-ES2L MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/gigabyte/ga-g41m-es2l +F: src/mainboard/gigabyte/ga-g41m-es2l/ GIGABYTE GA-H61M SERIES MAINBOARDS M: Angel Pons S: Maintained -F: src/mainboard/gigabyte/ga-h61m-series +F: src/mainboard/gigabyte/ga-h61m-series/ @@ -273,7 +273,7 @@ F: src/mainboard/google/stout/ INTEL D510MO MAINBOARD M: Damien Zammit S: Odd Fixes -F: src/mainboard/intel/d510mo +F: src/mainboard/intel/d510mo/ INTEL STRAGO MAINBOARD M: Hannah Williams @@ -314,7 +314,7 @@ LIBRETREND LT1000 MAINBOARD M: Piotr Król M: Michał Żygowski S: Maintained -F: src/mainboard/libretrend/lt1000 +F: src/mainboard/libretrend/lt1000/ OCP DELTALAKE MAINBOARD @@ -325,7 +325,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Supported -F: src/mainboard/ocp/deltalake +F: src/mainboard/ocp/deltalake/ OCP TIOGAPASS MAINBOARD M: Jonathan Zhang @@ -335,7 +335,7 @@ M: Morgan Jang M: Ryback Hung < M: Bryant Ou S: Maintained -F: src/mainboard/ocp/tiogapass +F: src/mainboard/ocp/tiogapass/ @@ -375,14 +375,14 @@ PRODRIVE HERMES MAINBOARD M: Christian Walter M: Patrick Rudolph S: Maintained -F: src/mainboard/prodrive/hermes +F: src/mainboard/prodrive/hermes/ PURISM MAINBOARDS M: Matt DeVillier S: Supported -F: src/mainboard/purism +F: src/mainboard/purism/ @@ -556,8 +556,8 @@ M: Marshall Dawson M: Felix Held M: Jason Glenesk S: Maintained -F: src/soc/amd/picasso -F: src/vendorcode/amd/fsp/picasso +F: src/soc/amd/picasso/ +F: src/vendorcode/amd/fsp/picasso/ INTEL APOLLOLAKE_SOC M: Andrey Petrov @@ -569,8 +569,8 @@ M: Piotr Król M: Michał Żygowski M: Frans Hendriks S: Maintained -F: /src/soc/intel/braswell -F: /src/vendorcode/intel/fsp/fsp1_1/braswell +F: /src/soc/intel/braswell/ +F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ INTEL Xeon Sacalable Processor Family M: Jonathan Zhang @@ -581,13 +581,13 @@ M: Ryback Hung < M: Bryant Ou S: Supported F: src/soc/intel/xeon_sp -F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp -F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ MEDIATEK SOCS M: Hung-Te Lin S: Supported -F: src/soc/mediatek +F: src/soc/mediatek/ ORPHANED ARM SOCS S: Orphaned @@ -615,13 +615,13 @@ F: payloads/coreinfo/ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer M: Martin Roth -F: payloads/external +F: payloads/external/ LINUXBOOT PAYLOAD INTEGRATION M: Christian Walter M: Marcello Sylvester Bauer S: Supported -F: payloads/external/LinuxBoot +F: payloads/external/LinuxBoot/ ################################################################################ # Utilities @@ -751,7 +751,7 @@ TPM SUPPORT M: Christian Walter S: Supported F: src/drivers/*/tpm/ -F: src/security/tpm +F: src/security/tpm/ SUPERIOS & SUPERIOTOOL M: Felix Held @@ -769,7 +769,7 @@ ELTAN VENDORCODE M: Frans Hendriks M: Wim Vervoorn S: Maintained -F: src/vendorcode/eltan +F: src/vendorcode/eltan/ MISSING: TIMERS / DELAYS From fee69744527773bed795ec829c212fdc8d9104bd Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 30 Nov 2020 07:57:06 +0100 Subject: [PATCH 28/44] mb/kontron/mal10/Kconfig: Reorder selects alphabetically Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48140 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/kontron/mal10/Kconfig | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig index 1705b9109c..f53746d7a9 100644 --- a/src/mainboard/kontron/mal10/Kconfig +++ b/src/mainboard/kontron/mal10/Kconfig @@ -2,18 +2,18 @@ if BOARD_KONTRON_COME_MAL10 config BOARD_SPECIFIC_OPTIONS def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_NCT7802Y + select EC_KONTRON_KEMPLD select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT - select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_16384 - select ONBOARD_VGA_IS_PRIMARY - select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_CRB_TPM - select EC_KONTRON_KEMPLD - select DRIVERS_I2C_NCT7802Y + select MAINBOARD_HAS_LIBGFXINIT + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE config MAINBOARD_DIR string From 45dc92a8c2e697411cb91bf255506575dd48afba Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Mon, 30 Nov 2020 08:20:19 +0100 Subject: [PATCH 29/44] mb/kontron/mal10: Use the system library for headers Use the system library for header files instead of relative filesystem paths. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48141 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c | 2 +- src/mainboard/kontron/mal10/variants/mal10/gpio.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c index f1f93bf4fc..674b209317 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/carrier/gpio.h" +#include static const struct pad_config gpio_table[] = { PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c index 1e88e38e5f..3986776870 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/gpio.c +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "include/variant/gpio.h" +#include static const struct pad_config gpio_table[] = { /* SPI */ From a1695504799f733c2fb1f030d1313535bbb5b065 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 1 Dec 2019 07:23:59 +0100 Subject: [PATCH 30/44] cpu/x86/sipi: Add x86_64 support Enter long mode on secondary APs. Tested on Lenovo T410 with additional x86_64 patches. Tested on HP Z220 with additional x86_64 patches. Still boots on x86_32. Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/45187 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Tim Wawrzynczak --- src/cpu/x86/64bit/entry64.inc | 10 ++++++++++ src/cpu/x86/sipi_vector.S | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc929..70255173f1 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -16,7 +16,12 @@ #endif #include +#if defined(__RAMSTAGE__) +#include +#else #include +#endif + setup_longmode: /* Get page table address */ @@ -42,7 +47,12 @@ setup_longmode: movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ +#if defined(__RAMSTAGE__) + ljmp $RAM_CODE_SEG64, $__longmode_start +#else ljmp $ROM_CODE_SEG64, $__longmode_start + +#endif .code64 __longmode_start: diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 054f30d2c4..61d9e34466 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -5,6 +5,8 @@ #include #include +#define __RAMSTAGE__ + /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into * C code. */ @@ -192,11 +194,24 @@ load_msr: mov %eax, %cr4 #endif +#ifdef __x86_64__ + /* entry64.inc preserves ebx. */ +#include + + mov %rsi, %rdi /* cpu_num */ + + movl c_handler, %eax + call *%rax +#else /* c_handler(cpu_num), preserve proper stack alignment */ sub $12, %esp push %esi /* cpu_num */ + mov c_handler, %eax call *%eax +#endif + + halt_jump: hlt jmp halt_jump From e2ce56928c11417114906a1dae2b12a3977bd39e Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 19 Nov 2020 16:53:14 -0700 Subject: [PATCH 31/44] mb/google/zork: Mark RW_MRC_CACHE as "Preserve" AGESA checks to make sure that the firmware version reading the MRC cache is the same version that wrote it, so it doesn't need to be erased during a firmware update. BUG=b:173724014 TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was not erased BRANCH=Zork Signed-off-by: Martin Roth Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/47776 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Felix Held --- src/mainboard/google/zork/chromeos.fmd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd index 7c2b95b6ec..be43e8a02d 100644 --- a/src/mainboard/google/zork/chromeos.fmd +++ b/src/mainboard/google/zork/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE 64K + RW_MRC_CACHE(PRESERVE) 64K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) From a99f61fec41f22c6c518d53078c322ca9891884c Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Mon, 30 Nov 2020 19:49:16 +0530 Subject: [PATCH 32/44] mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Ronak Kanabar Reviewed-by: Karthik Ramasubramanian --- .../intel/jasperlake_rvp/chromeos.fmd | 49 ++++++++++--------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 57be7f19e9..e4e0b242e0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,37 +1,38 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x12ffc0 - RW_FWID_A@0x13ffc0 0x40 - ME_RW_A(CBFS)@0x140000 0x190000 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x12ffc0 - RW_FWID_B@0x13ffc0 0x40 - ME_RW_B(CBFS)@0x140000 0x190000 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x30000 - WP_RO@0x600000 0x400000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 From 983ea18f179bb71b837907c81a5d394ad274ea84 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:33:41 +0100 Subject: [PATCH 33/44] cpu/intel/microcode: Mark assemblycode as 32bit Allows to compile the file under x86_64 without errors. The caller has to make sure to call the functions while in protected mode, which is usually the case in early bootblock. Change-Id: Ic6d98febb357226183c293c11ba7961f27fac40c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48164 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/cpu/intel/microcode/microcode_asm.S | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a5ed..5173ae5a0c 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -43,6 +43,7 @@ * if the revision of the update is newer than what is installed */ +.code32 .section .text .global update_bsp_microcode From 429c77a5e3ffab99c7a637d9ed0793df9f0319e3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:35:43 +0100 Subject: [PATCH 34/44] cpu/x86/early_reset: Mark assemblycode as 32bit Allows to compile the file under x86_64 without errors. The caller has to make sure to call the functions while in protected mode, which is usually the case in early bootblock. Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48165 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/cpu/x86/early_reset.S | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52a6d..07e63f42de 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -7,6 +7,7 @@ #include +.code32 .section .text .global check_mtrr From 2dbbb83ae4823db40ee9cca2016bb21fb2bc6bb4 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:38:11 +0100 Subject: [PATCH 35/44] lib/reg_script: Add cast to fix compilation on x86_64 Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48166 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/lib/reg_script.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68cd0e..bad9d9c53e 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx) switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } From 3805354ff9a47d846b8b2667c21a0d662780f9e8 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:42:24 +0100 Subject: [PATCH 36/44] soc/intel/common/block/systemagent: Fix compilation on x86_64 Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48167 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/common/block/systemagent/systemagent_early.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 53d6077e5f..ca11ee612a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -95,8 +95,8 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } From 90fda02f60309e0b843c805026d6a2978d9bd73d Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:44:17 +0100 Subject: [PATCH 37/44] drivers/intel/fsp2_0/notify: Fix compilation under x86_64 Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48168 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/drivers/intel/fsp2_0/notify.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf1281e..ee04630ca1 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -57,7 +57,7 @@ static void fsp_notify(enum fsp_notify_phase phase) static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); From 0e3884cfffec6e8edc9d29ee21820d896a9fa2be Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:44:40 +0100 Subject: [PATCH 38/44] drivers/aspeed/common/ast: Fix compilation under x86_64 Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48169 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/drivers/aspeed/common/ast_mode_corebootfb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index bf974ffffe..bb30d20acd 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -32,7 +32,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc) return -ENOMEM; } - fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095); ast_set_offset_reg(crtc); ast_set_start_address_crt1(ast, fb->mmio_addr); @@ -230,7 +230,7 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags) set_vbe_mode_info_valid(&edid, fb.mmio_addr); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); return 0; } From 2b77112e66d9d1678e68b7513bc916d49230993f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:52:42 +0100 Subject: [PATCH 39/44] soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support Doesn't affect x86_32. Tested on Intel Skylake. Boots into bootblock and console is working. Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/car/cache_as_ram.S | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc65c1..167342f12e 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include #include +.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -161,6 +162,15 @@ car_init_done: /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp /* push TSC value to stack */ @@ -168,6 +178,7 @@ car_init_done: pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_carstage: post_code(0x2A) From ed5835a04dce6d9f62d5db1ae22fe579e8efe08a Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:53:52 +0100 Subject: [PATCH 40/44] soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48171 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cpu/car/exit_car.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 9480a5a9c6..191232a3b0 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -28,7 +28,11 @@ chipset_teardown_car: * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. */ +#if ENV_X86_64 + pop %rbx +#else pop %ebx +#endif /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx @@ -95,4 +99,8 @@ car_nem_enhanced_teardown: #endif /* Return to caller. */ +#if ENV_X86_64 + jmp *%rbx +#else jmp *%ebx +#endif From ee38ccecf83f5ca29076d81fece1b43eed7a43a0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 30 Nov 2020 13:54:26 +0100 Subject: [PATCH 41/44] soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/common/block/smm/smihandler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa796..dc32970267 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -304,7 +304,7 @@ static void southbridge_smi_store( reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } @@ -409,7 +409,7 @@ void smihandler_southbridge_pm1( if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - pmc_disable_pm1_control(-1UL); + pmc_disable_pm1_control(~0); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } From 9bc16ed856581676d011759c4c8ced3001a9ec16 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 30 Nov 2020 18:06:35 +0100 Subject: [PATCH 42/44] soc/amd/picasso/aoac: fix typo in comment The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit, so the comment should be that it powers off the devices. Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/aoac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 1f7dcb02e4..f9fe0e2205 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -45,7 +45,7 @@ void power_off_aoac_device(unsigned int dev) { uint8_t byte; - /* Power on the UART and AMBA devices */ + /* Power off the UART and AMBA devices */ byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte &= ~FCH_AOAC_PWR_ON_DEV; aoac_write8(AOAC_DEV_D3_CTL(dev), byte); From 0d57f42e830a3a4b62764909e0a7964fcad24112 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 30 Nov 2020 20:26:38 +0100 Subject: [PATCH 43/44] soc/amd/picasso/aoac: make aoac_devs array unsigned The numbers in the array are unsigned, so use an unsigned type there. Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/picasso/aoac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index f9fe0e2205..00f26fe48e 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -21,7 +21,7 @@ * waiting for each device to become available, a single delay will be * executed. The console UART is handled separately from this table. */ -const static int aoac_devs[] = { +const static unsigned int aoac_devs[] = { FCH_AOAC_DEV_AMBA, FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, From ab0d85c9875dc83f8aee37bcb18eb834cfb2a238 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 30 Nov 2020 17:27:30 +0100 Subject: [PATCH 44/44] soc/amd/stoneyridge: align AOAC code with Picasso In commit 09d50671e6b43c23853a91ff4d6fb26c1e7e17a1 the AOAC code was reworked for Picasso and this patch ports this back to Stoneyridge to facilitate factoring out the functionality into common code. Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48181 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- .../amd/stoneyridge/include/soc/southbridge.h | 39 ++++++---------- src/soc/amd/stoneyridge/southbridge.c | 45 +++++++++---------- 2 files changed, 36 insertions(+), 48 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index cbd9caad95..9450a92723 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -190,16 +190,20 @@ #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -#define FCH_AOAC_D3_CONTROL_USB2 0x64 -#define FCH_AOAC_D3_CONTROL_USB3 0x6e +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C0 5 +#define FCH_AOAC_DEV_I2C1 6 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_USB2 18 +#define FCH_AOAC_DEV_USB3 23 + /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) @@ -209,16 +213,6 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -#define FCH_AOAC_D3_STATE_USB2 0x65 -#define FCH_AOAC_D3_STATE_USB3 0x6f /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) @@ -292,11 +286,6 @@ void soc_enable_psp_early(void); #define RST_CMD BIT(2) #define SYS_RST BIT(1) -struct stoneyridge_aoac { - int enable; - int status; -}; - typedef struct aoac_devs { unsigned int :5; unsigned int ic0e:1; /* 5: I2C0 */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 267f747b4f..05f3072edd 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,14 +31,13 @@ * waiting for each device to become available, a single delay will be * executed. */ -static const struct stoneyridge_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } +static const unsigned int aoac_devs[] = { + FCH_AOAC_DEV_UART0 + CONFIG_UART_FOR_CONSOLE * 2, + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C0, + FCH_AOAC_DEV_I2C1, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, }; static int is_sata_config(void) @@ -146,21 +145,21 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(unsigned int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -174,14 +173,14 @@ void enable_aoac_devices(void) int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); } while (!status); } @@ -545,14 +544,14 @@ static void set_sb_final_nvs(void) if (gnvs == NULL) return; - gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); - gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); - gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); + gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C0); + gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); + gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_DEV_USB2); + gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_DEV_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0;