- fix SMM code relocation race
- make SMM relocation debugging Kconfig accessible Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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src/Kconfig
12
src/Kconfig
@ -560,6 +560,18 @@ config DEBUG_SMI
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If unsure, say N.
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If unsure, say N.
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config DEBUG_SMM_RELOCATION
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bool "Debug SMM relocation code"
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default n
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depends on HAVE_SMI_HANDLER
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help
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This option enables additional SMM handler relocation related
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debug messages.
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Note: This option will increase the size of the coreboot image.
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If unsure, say N.
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config X86EMU_DEBUG
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config X86EMU_DEBUG
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bool "Output verbose x86emu debug messages"
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bool "Output verbose x86emu debug messages"
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default n
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default n
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@ -1,7 +1,7 @@
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/*
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/*
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2008-2010 coresystems GmbH
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*
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*
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* This program is free software; you can redistribute it and/or
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* modify it under the terms of the GNU General Public License as
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@ -24,12 +24,15 @@
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// FIXME: Is this piece of code southbridge specific, or
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// FIXME: Is this piece of code southbridge specific, or
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// can it be cleaned up so this include is not required?
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// can it be cleaned up so this include is not required?
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// It's needed right now because we get our PM_BASE from
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// It's needed right now because we get our DEFAULT_PMBASE from
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// here.
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// here.
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#if defined(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
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#include "../../../southbridge/intel/i82801gx/i82801gx.h"
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#include "../../../southbridge/intel/i82801gx/i82801gx.h"
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#elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
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#undef DEBUG_SMM_RELOCATION
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#include "../../../southbridge/intel/i82801dx/i82801dx.h"
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//#define DEBUG_SMM_RELOCATION
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#else
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#error "Southbridge needs SMM handler support."
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#endif
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#define LAPIC_ID 0xfee00020
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#define LAPIC_ID 0xfee00020
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@ -125,7 +128,7 @@ smm_relocate:
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addr32 movl %eax, (%ebx)
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addr32 movl %eax, (%ebx)
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/* The next section of code is hardware specific */
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/* The next section of code is potentially southbridge specific */
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/* Clear SMI status */
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/* Clear SMI status */
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movw $(DEFAULT_PMBASE + 0x34), %dx
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movw $(DEFAULT_PMBASE + 0x34), %dx
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@ -143,8 +146,9 @@ smm_relocate:
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orl $(1 << 1), %eax
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orl $(1 << 1), %eax
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outl %eax, %dx
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outl %eax, %dx
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/* End of hardware specific section. */
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/* End of southbridge specific section. */
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#ifdef DEBUG_SMM_RELOCATION
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#if defined(CONFIG_DEBUG_SMM_RELOCATION) && CONFIG_DEBUG_SMM_RELOCATION
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/* print [SMM-x] so we can determine if CPUx went to SMM */
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/* print [SMM-x] so we can determine if CPUx went to SMM */
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movw $CONFIG_TTYS0_BASE, %dx
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movw $CONFIG_TTYS0_BASE, %dx
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mov $'[', %al
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mov $'[', %al
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@ -86,6 +86,7 @@ extern void i82801dx_enable(device_t dev);
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#define PCICMD 0x04
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#define PCICMD 0x04
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#define PMBASE 0x40
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#define PMBASE 0x40
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#define PMBASE_ADDR 0x0400
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#define PMBASE_ADDR 0x0400
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#define DEFAULT_PMBASE PMBASE_ADDR
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#define ACPI_CNTL 0x44
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0x4E
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58
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#define GPIO_BASE 0x58
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@ -335,11 +335,13 @@ static void smm_install(void)
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void smm_init(void)
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void smm_init(void)
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{
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{
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// FIXME is this a race condition?
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/* Put SMM code to 0xa0000 */
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smm_relocate();
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smm_install();
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smm_install();
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// We're done. Make sure SMIs can happen!
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/* Put relocation code to 0x38000 and relocate SMBASE */
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smm_relocate();
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/* We're done. Make sure SMIs can happen! */
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smi_set_eos();
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smi_set_eos();
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}
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}
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@ -335,11 +335,13 @@ static void smm_install(void)
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void smm_init(void)
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void smm_init(void)
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{
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{
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// FIXME is this a race condition?
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/* Put SMM code to 0xa0000 */
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smm_relocate();
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smm_install();
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smm_install();
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// We're done. Make sure SMIs can happen!
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/* Put relocation code to 0x38000 and relocate SMBASE */
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smm_relocate();
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/* We're done. Make sure SMIs can happen! */
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smi_set_eos();
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smi_set_eos();
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}
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}
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