soc/intel/skylake: search for PME wake event on all root ports
Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist. Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
committed by
Patrick Georgi
parent
1b79b86def
commit
bc36e298f9
@@ -149,6 +149,18 @@
|
||||
#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d
|
||||
#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e
|
||||
#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a
|
||||
#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b
|
||||
|
||||
struct elog_event_data_wake {
|
||||
u8 source;
|
||||
|
Reference in New Issue
Block a user