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mainboard/google/fizz: Enable Devslp for SATA port 1

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This patch is to enable the support of device sleep
for SATA port 1 and disable unused SATA port 0.

BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.

Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Gaggery Tsai
2017-09-29 13:40:04 +08:00
committed by Furquan Shaikh
parent 5b9a7f5217
commit bc37c67837
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/fizz/devicetree.cb
View File

@@ -56,8 +56,8 @@ chip soc/intel/skylake
register "EnableSata" = "1" register "EnableSata" = "1"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataMode" = "1" register "SataMode" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "EnableAzalia" = "1" register "EnableAzalia" = "1"
register "DspEnable" = "1" register "DspEnable" = "1"
register "IoBufferOwnership" = "3" register "IoBufferOwnership" = "3"

2
src/mainboard/google/fizz/gpio.h
View File

@@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = {
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, /* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
NF1), /* DB_PCIE_SATA#_DET */ NF1), /* DB_PCIE_SATA#_DET */
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), /* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
/* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* TP328 */
/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), /* CPU_GP1 */ PAD_CFG_NC(GPP_E7),